Quntittive Stuies of Impct of 3D IC Design on Repeter Usge Json Cong, Chunyue Liu, Guojie Luo Computer Science Deprtment, UCLA {cong, liucy, gluo}@cs.ucl.eu Abstrct: In this pper, we present our quntittive stuies of the impct of 3D IC esign on repeter usge. The repeter usge is estimte by the interconnect optimizer IPEM in the post-plcement/ pre-routing stge, where the 2D n 3D plcement re generte by stte-of-rt mixe-size plcers mpl6 n mpl-3d. Experiments on set of rel inustril esigns show tht, through 3D plcement, the totl number of repeters use in the on-chip interconnections cn be reuce by 19.74% n 51.41% on verge with 3 lyers n 4 lyers of 3D IC esigns, respectively. I. INTRODUCTION Three-imensionl (3D) IC technologies promise to further increse integrtion ensity, beyon Moore's Lw, n offer the potentil to significntly reuce interconnect elys n improve system performnce. Furthermore, the shortene wirelength, especilly tht of the clock net, lessens the power consumption of the circuit. 3D IC technologies lso provie flexible wy to crry out the heterogeneous system-on-chip (SoC) esign by integrting isprte technologies, such s memory n logic circuits, rio frequency (RF) n mixe signl components, optoelectronic evices, etc., onto ifferent lyers of 3D IC. Since 3D IC technology enbles n itionl egree of freeom for circuit esign, previous experiences on 2D esigns my not be vli n nee to be refreshe. To etermine the system performnce n relibility, it is pointe out tht interconnect hs become the ominting fctor [1][2]. Thus, interconnect-centric nlysis is very importnt in stuying the impct of 3D IC technology. Quntittive stuies of wirelength reuction from 3D IC technology hve been one for stnr cell circuits [8][10]. The stuy [7] gives n erly look on the promise of 3D IC technology. It roughly estimtes both the 2D n 3D wirelength istributions by Rent s rule, n shows tht the wiring reuirement is significntly reuce for the globl wires in 3D ICs. The stuy in [8] shows tht there is bout 50% wirelength reuction of 4-lyer 3D circuits compre to tritionl 2D implementtions. It supports the eclrtion in [14] tht the iel wirelength reuction, which ignores the cost of TS vis, is the squre root of the number of vilble evice lyers. The stuy in [10] performs extensive experiments on the reltions mong wirelength, TS vi number n temperture with ifferent number of evice lyers. It shows tht scrificing only 2% of the iel wirelength reuction cn chieve 46% TS vi number reuction for 4-lyer 3D circuits. It lso shows tht temperture cn be reuce by bout 20% with only 1% less of the iel wirelength reuction n 10% more TS vis. However, there is lck of quntittive stuy on the impct of 3D IC technology to the repeter usge, which hs increse rmticlly for 2D esigns [1][2][3]. It is known tht ely of n unbuffere segment of wire is qurtic to the wirelength, n repeters re use to linerize the ely. Repeters re very effective in reucing long interconnect, but they lso consume gret mount of sttic n ynmic power. Therefore, it is importnt to quntify the benefit of 3D esign on repeter reuction. In this pper, we perform quntittive stuies on repeters usge ue to the scling in the 3 r imension, which hve ifferent number evice lyers from 1 to 4. The repeter numbers re estimte in the post-plcement/pre-routing stge. The plcements for 1 evice lyer circuits re one by mpl6 [4], n the plcements for 2 to 4 evice lyer circuits re one by mpl-3d [8]. The interconnection ely is estimte by the tool IPEM [11]. From the experimentl results, we hve observe consierble ecrese of repeters which in turn reuce the power n re. II. 3D PLACEMENT The quntittive stuies of repeter estimtion re performe t the post-plcement stge. In this section we will first escribe our plcement methos. Seprte 2D n 3D plcements re one by the stte-of-the-rt 2D n 3D plcers, mpl6 n mpl3d, respectively. A. 2D Plcer Recent nlyticl globl plcers show very successful results in both qulity n sclbility [4][16][17]. Menwhile, mny stuies [18] show tht multilevel lgorithm is promising technique to hnle lrge-scle problems. Therefore, we use multilevel nlyticl plcer for high qulity 2D
plcement. The nlyticl plcement engine [4][9] is to solve the plcement problem by nonliner optimiztion lgorithms, which is formulte in Figure 1. The ifferentibility of the objective n constrint functions is require. The objective of hlf-perimeter wirelength is pproximte by replcing the mx function with log-sum-exp function [1]. The non-overlp constrints re replce by ensity constrints, n the ensity function is smoothe by Helmholtz eqution [4] for ifferentibility. The multilevel frmework [4] consists of corsening, relxtion n interpoltion, s showe in Figure 2. Corsening is to buil hierrchy of the netlist by clustering. The corsene netlist is still netlist so tht plcement problem is solve t ech level. The corsest netlist is plce first n then the solution is interpolte to the finer netlist s n initil solution. This initil solution is relxe by the nlyticl plcement engine referre bove. The solution t ech level is interpolte to finer level until solution t the finest level is obtine. Aitionl cycles of such process my be pplie. Legliztion n etile plcement [6] re pplie fter the globl plcement. minimize WireLength( xy, ) subject to Density Trget_Density i, j Figure 1 Nonliner Progrmming one first on region K times lrger thn the plcement region on one lyer in the 3D IC. The 2D plcement region is then shrinke uniformly to meet the 3D plcement region, n remin the reltive loctions of the plce cells. The lyer ssignment of these cells is etermine by moifie Tetris legliztion, n is further refine by RCN grph. Lyer-by-lyer etile plcement is pplie to obtin finl 3D plcement. The results [8] show tht the wirelength of 4-lyer 3D IC cn be s short s 50% of 2D implementtion. 2D Plcement 2D to 3D Trnsformtion Lyer Ressignment through RCN Grph 2D Detile Plcement for Ech Lyer,b,c, c b c b Figure 3 Trnsformtion-bse 3D Plcer Stcking Legliztion Figure 2 Multilevel Frmework B. 3D Plcer To tke vntge of the existing high-qulity 2D plcer, we use the 3D plcer bse on 2D to 3D trnsformtion [8]. It is therml-wre 3D plcer proviing tre-offs between the wirelength n the number of Through-Silicon (TS) vis. The trnsformtion methos inclue locl stcking, foling-2, foling-4, n winow-bse stcking/foling. Among these trnsformtion methos, locl stking [8] performs best mong in terms of wirelength, if ignoring the cost of TS vis. A trnsformtion frmework with the locl stcking metho is showe in Figure 3. For K-lyer 3D IC, 2D plcement is III. REPEATER ESTIMATION After the plcement, in this section we will introuce our pproch of repeter estimtion. To optimize the repeter insertion in the on-chip interconnections for minimum ely n re, we evelope IPEM [11], which cn provie set of proceures tht estimte interconnect performnce uner vrious performnce optimiztion lgorithms for eep submicron technology. Although mny interconnect optimiztion lgorithms, such s wire sizing n spcing, optiml buffer insertion, wire sizing optimiztion, globl interconnect sizing n spcing n simultneous river, buffer, n interconnect sizing, hve been intensively investigte previously, these pproches re generlly evelope for physicl level, i.e., they re not efficient to be use in higher level esign n synthesis. However the interconnection shoul be consiere s erly s possible for esign convergence. Uner this circumstnce, the interconnect estimtion moeling techniques is propose to get fst n ccurte estimtion of the optiml interconnect ion performnce uner vrious optimiztion lgorithms. IPEM is such tool tht through opting simple close-form formule or computtionl proceures, it cn provie fst yet ccurte estimtion of interconnection ely n re. As cn be seen in
Figure 4, when provie the river effective resistnce of the input stge G 0, the river effective resistnce of G, interconnect wirelength l n loing cpcitnce C L, IPEM cn provie the optiml ely n re of the bol interconnection wire through optimiztion lgorithms incluing OWS (Optiml Wire Sizing), SDWS (Simultneous Driver n Wire Sizing), BIWS (Buffer Insertion n Wire Sizing) n BISWS (Buffer Insertion, Sizing n Wire Sizing), etc. Pckge trgete t extensive interconnect lyout optimiztion. Figure 5 shows the comprison results uner 0.18 um technology for OWS between IPEM enote by the squres n Trio enote by the soli points, with R = r g /100, C L = c g *100, where r g n c g re the output resistnce n the input cpcitnce of minimum evice respectively. Figure 4 IPEM Interconnection Optimiztion Here, we give n exmple of IPEM uner the OWS optimiztion. For OWS, the size of the river G in Figure 2 is fixe. Let T ows (R, l, C L ) be the ely uner OWS for n interconnect l with river resistnce R n loing cpcitnce C L. Through extensive nlyticl n numericl stuies on the complex optiml wire shping function, the following simple close-form formule uner OWS is obtine. T ( R, l, C ) ( l / W ( l) 2 l / W ( l) ows L R c R rc c l )* l f f 2 1 2 1 2 (1) 1 1 rc (2) 4 1 rc 2 (3) 2 RC L Where r is the sheet resistnce, c is the unit re cpcitnce, c f is the unit effective-fringing cpcitnce, n W(x) is Lmbert s W function efine s the vlue of w tht stisfies we w = x. The close-form re estimtion formul is obtine s shown in (4). r( c fl 2 CL) Aows ( R, l, CL ) l (4) 2Rc The other optimiztion techniques of IPEM cn be foun in [11]. Experiment results [11] show tht IPEM hs n ccurcy of 90% on verge, with running spee of 1000 times fster thn Trio [12] which is Tree-Repeter-Interconnect Optimiztion Figure 5 Comprison of Trios n IPEM for OWS IV. EXPERIMENTAL SETUP AND RESULTS The experiments re performe on the IBM- PLACE benchmrks [13]. Since these benchmrks o not hve source/sink pin informtion, to get reltively more ccurte informtion of the net wirelength, we use the length of minimum-wirelength-tree of net to estimte the optiml number of repeters require in this net inste of using the hlf-bouning box metho use in [8]. The rectiliner Steiner miniml tree hs been wiely use in erly esign stges such s physicl synthesis, floorplnning, interconnect plnning n plcement to estimte wirelength, routing congestion n interconnect ely. It uses the minimum wirelength eges to connect noes in given net. In this pper, rectiliner Steiner tree construction pckge FLUTE [14] is use to clculte the Steiner wirelength tree in orer to estimte the repeter insertion without performing the etile routing. FLUTE is bse on pre-compute lookup tble to mke the Steiner minimum tree construction fst n ccurte for low egree nets. For high egree nets, the net is ivie into severl low egree nets until the tble cn be use. To ccurtely estimte the ely n re of the TS vi resistnce n cpcitnce, we use the pproch in [15] to moel the TS vi s length of wire. Becuse of its lrge size, the TS vi hs gret self-cpcitnce. By simultions on ech vi n the lengths of metl-2 wires in ech lyer, the uthors in
[15] pproximte the cpcitnce of n TS vi with 3 μm thickness s roughly 8~20 μm of wire. The resistnce is less significnt becuse of the lrge cross-sectionl re of ech vi (bout 0.1 Ω per vi), which is equivlent to bout 0.2 μm of metl-2 wire. We use 3D IC technology by MIT Lincoln lb n the minimum istnce between jcent lyers is 2~3.45 μm. Thus, we cn pproximtely trnsform ll the TS vis between jcent lyers s 14 μm wires (n verge vlue of 8~20 μm). This vlue is ouble when the vi is going through two lyers. Since FLUTE cn only generte 2D minimum wirelength tree, in orer to trnsform it to 3D tree for our 3D esigns, we mke the following ssumptions: 1) Assume tht ll the tree wires re plce in mile lyer of the 3D stck lyers, 2) The pins in other lyers use TS vis to connect to the tree on the mile lyer. This ssumption minimizes the totl tritionl wires in net but overestimtes the totl number of TS vis. However, it cn provie us more ccurte informtion of the totl net wirelength compre to the 3D vi n wirelength estimtion metho use in [8] where the number of vi is simply set s the number of the lyers the net spns. The experiments re performe uner 32 nm technology. The technology prmeters we use to configure IPEM re liste in Tble 1. We run FLUTE n IPEM for ech net in ech benchmrk. Tble 1 Technology Prmeters Tble 2 shows the comprison results for IBM- PLACE benchmrks. As cn be seen, by using 3D plcement with 3 lyers, the totl wirelength cn be reuce by 15.49% n the number of repeters use in interconnection cn be reuce by 19.74% respectively on verge compre to the cse of 2D esign. Furthermore, when 4 lyers re use in the 3D plcement, the wirelength cn be further reuce by 42.13% n the number of repeters cn be reuce by 51.41%. As shown in Tble 2, the reuction in the number of repeters through 3D IC compre to tht of the 2D cses is lwys more thn the reuction of the totl wirelength. This is becuse incresing the number of lyers will efficiently ecrese the length of the nets with lrge minimum wirelength tree, n nets with very smll minimum wirelength tree lwys o not nee repeters. As cn be seen in the IPEM results, wires less thn 500 um usully result in 0 repeters. Therefore, by reucing the nets with lrge length of the minimum wirelength tree, we cn significntly reuce the number repeters n the re/power of the on-chip interconnection. V. CONCLUSION Using 3D technology couple with stte-of-rt 3D plcement tool, we hve observe significntly reuction in the number of repeters use in the on-chip interconnections. By reucing the repeter usge, we expect to chieve consierble sving of the power n re of the on-chip interconnections. ACKNOWLEDGEMENTS This work is prtilly supporte by IBM uner DARPA subcontrct n by GRC uner contrct 2005-TJ-1317. REFERENCE [1] J. Cong, "An Interconnect-Centric Design Flow for Nnometer Technologies", Proceeings of the IEEE, vol. 89, no. 4, pp 505-528, April 2001. [2] J. Cong, L. He, K. Y. Khoo, C. K. Koh n Z. Pn "Interconnect Design for Deep Submicron ICs," Proc. IEEE Int'l Conf. on Computer-Aie Design, Sn Jose, Cliforni, pp. 478-485, Nov. 1997. [3] P. Sxen, N. Menezes, P. Cocchini, n D.A. Kirkptrick, "Repeter scling n its impct on CAD," IEEE Trnsctions on Computer-Aie Design of Integrte Circuits n Systems, vol.23, no.4, pp. 451-463, April 2004. [4] J. Cong, T. Chn, J. Shinnerl, K. Sze n M. Xie, "mpl6: Enhnce Multilevel Mixe-size Plcement," Proceeings of the ACM Interntionl Symposium on Physicl Design, Sn Jose, CA, pp. 212-214, April 2006. [5] G.-J. Nm, ISPD 2006 Plcement Contest: Benchmrk Suite n Results, Proceeings of the 2006 Interntionl Symposium on Physicl Design, pp. 167-167, 2006. [6] J. Cong, M. Xie, A Robust Mixe-Size Legliztion n Detile Plcement Algorithm, IEEE Trnsctions on Computer-Aie Design of Integrte Circuits n Systems, vol.27, no.8, pp.1349-1362, Aug. 2008. [7] K. Bnerjee, S.J. Souri, P. Kpur, n K.C. Srswt, 3-D ICs: Novel Chip Design for Improving Deep-submicrometer Interconnect Performnce n Systems-on-chip Integrtion, Proceeings of the IEEE, vol. 89, no. 5, pp. 602-633, My 2001. [8] J. Cong, G. Luo, J. Wei, Y. Zhng, Therml-Awre 3D IC Plcement vi Trnsformtion, Proc. of the 12th Asi n South Pcific Design Automtion Conference, Yokohm, Jpn, pp. 780-785, Jn. 2007. [9] J. Cong n G. Luo, "Highly Efficient Grient Computtion for Density-Constrine Anlyticl Plcement Methos",
Proceeings of the 2008 ACM Interntionl Symposium on Physicl Design, Portln, Oregon, pp. 39-46, April 2008 [10] B. Goplen n S. Sptnekr, Plcement of 3D ICs with therml n interlyer vi consiertions, Proc. of the 44th nnul conference on Design utomtion, pp. 626-631, 2007. [11] J. Cong n D.Z. Pn, "Interconnect Estimtion n Plnning for Deep Submicron Designs", Proc. of Design Automtion Conference, New Orlens, LA., pp. 507-510, June, 1999 [12] J. Cong, L. He, C.K. Koh n Z. Pn, "Globl Interconnect Sizing n Spcing with Consiertion of Coupling Cpcitnce", ACM/IEEE Int'l Conf. on Computer-Aie Design, pp. 628-633, Dec. 1997 [13] http://er.cs.ucl.eu/benchmrks/ibm-plce/ [14] C. Chu, Y. Wong, "FLUTE: Fst Lookup Tble Bse Rectiliner Steiner Miniml Tree Algorithm for VLSI Design", IEEE Trnsctions on Computer-Aie Design of Integrte Circuits n Systems, Vol. 27, Issue 1, pp. 70-83, Jn. 2008 [15] W.R. Dvis; J. Wilson, S. Mick, etc., "Demystifying 3D ICs: the pros n cons of going verticl," IEEE Design & Test of Computers, Vol. 22, Issue 6, pp. 498-510, Nov.-Dec. 2005. [16] T.-C. Chen, Z.-W. Jing, T.-C. Hsu, H.-C. Chen, n Y.-W. Chng, "A High-qulity Mixe-size Anlyticl Plcer Consiering Preplce Blocks n Density Constrints," Proceeings of the 2006 IEEE/ACM Interntionl Conference on Computer-Aie Design, Sn Jose, CA, pp. 187-192, November 2006. [17] H. Eisenmnn n F. M. Johnnes, "Generic Globl Plcement n Floorplnning," Proceeings of the 35th Annul Conference on Design Automtion, Sn Frncisco, CA, pp. 269-274, June 1998. [18] Multilevel Optimiztion n VLSICAD, e. J. Cong n J.R. Shinnerl, Kluwer Acemic Publishers, Boston, 2002. [19] W. C. Nylor, R. Donelly, n L. Sh, Non-liner Optimiztion System n Metho for Wire Length n Dely Optimiztion for n Automtic Electric Circuit Plcer, US Ptent 6301693, October 2001. Tble 2 Results of the number of wirelength/repeters for IBM-PLACE Benchmrks 2D Plcement 3D Plcement (3 Lyers) 3D Plcement (4 Lyers) Benchmrks Totl Wire Totl Wire length (um) #Repeters Totl Wire length (um) #Repeters #Repeters length (um) Reuce Reuce Reuce Reuce ibm 01 5,340,531 5,241 5,705,513-6.83% 5,623-7.29% 3,690,917 30.89% 2,866 45.32% ibm 02 15,733,437 18,370 13,231,177 15.90% 14,674 20.12% 8,811,791 43.99% 8,543 53.49% ibm 03 15,624,821 18,023 11,654,377 25.41% 12,217 32.21% 8,941,162 42.78% 8,372 53.55% ibm 04 18,478,722 20,720 14,883,848 19.45% 15,508 25.15% 10,486,259 43.25% 9,382 54.72% ibm 05 41,260,244 52,740 33,841,068 17.98% 41,795 20.75% 28,683,802 30.48% 34,758 34.10% ibm 06 25,726,920 29,757 19,515,728 24.14% 20,601 30.77% 15,071,901 41.42% 14,366 51.72% ibm 07 40,571,536 48,630 30,162,968 25.65% 33,217 31.69% 22,374,322 44.85% 22,557 53.62% ibm 08 45,723,304 55,685 34,622,016 24.28% 39,096 29.79% 25,579,604 44.06% 26,682 52.08% ibm 09 36,590,608 42,210 27,722,182 24.24% 28,653 32.12% 21,091,114 42.36% 20,037 52.53% ibm 10 62,148,072 74,318 49,074,524 21.04% 54,361 26.85% 34,961,648 43.74% 35,428 52.33% ibm 11 43,441,568 47,504 42,149,136 2.98% 45,018 5.23% 24,954,992 42.56% 21,266 55.23% ibm 12 75,913,368 92,264 67,831,048 10.65% 80,047 13.24% 42,164,064 44.46% 44,254 52.04% ibm 13 71,395,456 84,036 67,278,656 5.77% 76,909 8.48% 40,258,068 43.61% 39,376 53.14% ibm 14 125,077,064 146,899 108,393,400 13.34% 121,384 17.37% 69,462,392 44.46% 67,215 54.24% ibm 15 165,876,560 201,767 149,695,664 9.75% 176,427 12.56% 93,114,488 43.87% 97,190 51.83% ibm 16 181,410,896 219,291 156,584,160 13.69% 180,619 17.64% 101,196,632 44.22% 103,891 52.62% ibm 17 266,743,968 336,971 224,178,208 15.96% 273,579 18.81% 146,224,448 45.18% 163,610 51.45% Averge 15.49% 19.74% 42.13% 51.41%