Resistor Network DC D DC DC Register D DC Register 8 Buffer D Data Data Buffer 4 FETURES DESCRIPTION Micropower Operation: 5 µ at 3 V V DD The is a low-power, quad channel, 8-bit Fast Update Rate: 88 ksps buffered voltage output DC. Its on-chip precision Per-channel Power-down Capability output amplifier allows rail-to-rail output swing to be achieved. The utilizes an I 2 C compatible Power-On Reset to Zero two wire serial interface supporting high-speed 2.7-V to 5.5-V nalog Power Supply interface mode with address support of up to four 8-bit Monotonic s for a total of 6 channels on the bus. I 2 C Interface Up to 3.4 Mbps The uses V DD and GND to set the output Data Transmit Capability range of the DC. The incorporates a On-Chip Output Buffer mplifier, Rail-to-Rail power-on-reset circuit that ensures that the DC Operation output powers up at zero volts and remains there until Double-Buffered Input Register a valid write takes place to the device. The contains a per-channel power-down feature, ac- ddress Support for up to Four s cessed via the internal control register, reducing the Synchronous Update Support for up to 6 current consumption of the device to 2 n at 5 V. Channels The low power consumption of this part in normal Operation From 4 C to 5 C operation makes it ideally suited to portable battery Small Lead MSOP Package operated equipment. The power consumption is less PPLICTIONS than 3mW at V DD = 5 V reducing to µw in power-down mode. Process Control TI offers a variety of data converters with I 2 C Data cquisition Systems interface. See DCx57x family of 6/2//8 bit, Closed-Loop Servo Control single and quad channel DCs. lso see DS7823 PC Peripherals and DS, 2-bit octal channel and 6-bit single channel DCs. Portable Instrumentation Buffer Control DD V D TUO V C TUO V B TUO V TUO V Power-Down Control Logic Register Control GND C2 I Block SD SCL QUD, 8-BIT, LOW-POWER, VOLTGE OUTPUT, I 2 C INTERFCE DIGITL-TO-NLOG CONVERTER SLS47 DECEMBER 23 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I 2 C is a trademark of Philips Corporation. PRODUCTION DT information is current as of publication date. Copyright 23, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SLS47 DECEMBER 23 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PCKGE/ORDERING INFORMTION () PRODUCT PCKGE PCKGE SPECIFICTION PCKGE ORDERING TRNSPORT MEDI DRWING TEMPERTURE MRKING NUMBER NUMBER RNGE -MSOP DGS 4 C TO +5 C D574 IDGS 8 Piece Tube IDGSR 25 Piece Tape and Reel () For the most current package and ordering information, see the Package Option ddendum at the end of this document, or see the TI website at. V OUT V OUT B GND V OUT C V OUT D. DGS PCKGE (TOPVIEW) 2 9 3 8 V DD 4 7 SD 5 6 SCL PIN DESCRIPTIONS PIN NME DESCRIPTION V OUT nalog output voltage from DC 2 V OUT B nalog output voltage from DC B 3 GND Ground reference point for all circuitry on the part 4 V OUT C nalog output voltage from DC C 5 V OUT D nalog output voltage from DC D 6 SCL Serial clock input 7 SD Serial data input and output 8 V DD nalog voltage supply input 9 Device address select - I 2 C Device address select - I 2 C BSOLUTE MXIMUM RTINGS () V DD to GND Digital input voltage to GND V OUT to GND Operating temperature range Storage temperature range Junction temperature range (T J max).3 V to +6 V.3 V to V DD +.3 V.3 V to V DD +.3 V 4 C to +5 C 65 C to +5 C +5 C Power dissipation: Thermal impedance (ΘJ) 27 C/W Thermal impedance (ΘJC) 77 C/W Lead temperature, soldering: Vapor phase (6s) 25 C Infrared (5s) 22 C () Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 2
SLS47 DECEMBER 23 ELECTRICL CHRCTERISTICS V DD = 2.7 V to 5.5 V, R L = 2 kω to GND; C L = 2 pf to GND; all specifications 4 C to +5 C, unless otherwise specified. STTIC PERFORMNCE () PRMETER TEST CONDITIONS MIN TYP MX UNITS Resolution 8 Bits Relative accuracy ±.5 ±.5 LSB Differential nonlinearity Specified monotonic by design ±.2 ±.25 LSB Zero-scale error 5 2 mv Full-scale error -.5 ±. % of FSR Gain error ±. % of FSR Zero code error drift ±7 µv/ C Gain temperature coefficient ± 3 ppm of FSR/ C OUTPUT CHRCTERISTICS (2) Output voltage range V DD V Output voltage settling time (full scale) R L = ; pf < C L < 2 pf 6 8 µs R L = ; C L = 5 pf 2 µs Slew rate V/µs dc crosstalk (channel-to-channel).25 LSB ac crosstalk (channel-to-channel) khz Sine Wave - db Capacitive load stability R L = 47 pf R L = 2 kω pf Digital-to-analog glitch impulse LSB change around major carry 2 nv-s Digital feedthrough.3 nv-s dc output impedance Ω Short-circuit current V DD = 5 V 5 m V DD = 3 V 2 m Power-up time Coming out of power-down mode, 2.5 µs V DD = +5 V LOGIC INPUTS (2) Coming out of power-down mode, 5 µs V DD = +3 V Input current ± µ V IN_L, Input low voltage.3xv DD V V IN_H, Input high voltage V DD = 3 V.7xV DD V Pin Capacitance 3 pf POWER REQUIREMENTS V DD 2.7 5.5 V I DD (normal operation), including reference current Excluding load current I DD @ V DD =+3.6V to +5.5V V IH = V DD and V IL =GND 6 9 µ I DD @ V DD =+2.7V to +3.6V V IH = V DD and V IL =GND 5 75 µ I DD (all power-down modes) POWER EFFICIENCY I DD @ V DD =+3.6V to +5.5V V IH = V DD and V IL =GND.2 µ I DD @ V DD =+2.7V to +3.6V V IH = V DD and V IL =GND.5 µ I OUT /I DD I LOD = 2 m, V DD = +5 V 93% TEMPERTURE RNGE Specified performance -4 +5 C () Linearity tested using a reduced code range of 48 to 447; output unloaded. (2) Specified by design and characterization, not production tested. 3
SLS47 DECEMBER 23 TIMING CHRCTERISTICS V DD = 2.7 V to 5.5 V, R L = 2 kω to GND; all specifications 4 C to +5 C, unless otherwise specified. SYMBOL PRMETER TEST CONDITIONS MIN TYP MX UNITS f SCL SCL clock frequency Standard mode khz Fast mode 4 khz High-Speed Mode, C B = pf max 3.4 MHz High-speed mode, C B = 4 pf max.7 MHz Bus free time between a Standard mode 4.7 µs t BUF STOP and STRT condition Fast mode.3 µs Standard mode 4. µs t HD ; t ST Hold time (repeated) STRT condition Fast mode 6 ns High-speed mode 6 ns t LOW t HIGH LOW period of the SCL clock HIGH period of the SCL clock Standard mode 4.7 µs Fast mode.3 µs High-speed mode, C B = pf max 6 ns High-speed mode, C B = 4 pf max 32 ns Standard mode 4. µs Fast mode 6 ns High-Speed Mode, C B = pf max 6 ns High-speed mode, C B = 4 pf max 2 ns Standard mode 4.7 µs t SU ; t ST Setup time for a repeated STRT condition Fast mode 6 ns High-speed mode 6 ns Standard mode 25 ns t SU ; t DT Data setup time Fast mode ns t HD ; t DT t RCL Data hold time Rise time of SCL signal High-speed mode ns Standard mode 3.45 µs Fast mode.9 µs High-speed mode, C B = pf max 7 ns High-speed mode, C B = 4 pf max 5 ns Standard mode ns Fast mode 2 +.C B 3 ns High-speed mode, C B = pf max 4 ns High-speed mode, C B = 4 pf max 2 8 ns Standard mode ns Rise time of SCL signal after a repeated STRT condition Fast mode 2 +.C B 3 ns t RCL and after an acknowledge High-speed mode, C B = pf max 8 ns t FCL t RD BIT Fall time of SCL signal Rise time of SD signal High-speed mode, C B = 4 pf max 2 6 ns Standard mode 3 ns Fast mode 2 +.C B 3 ns High-speed mode, C B = pf max 4 ns High-speed mode, C B = 4 pf max 2 8 ns Standard mode ns Fast mode 2 +.C B 3 ns High-speed mode, C B = pf max 8 ns High-speed mode, C B = 4 pf max 2 6 ns 4
LE LSB DLE LSB 224 92 6 28 96 64 32.5.5.5.25.25.5 TYPICL CHRCTERISTICS t T = +25 C, unless otherwise noted. Digital Input Code Digital Input Code 224 92 6 28 96 64 Channel = 5 V DD 255 32.5.5.5.25.25.5 255 LE LSB DLE LSB TIMING CHRCTERISTICS (continued) V DD = 2.7 V to 5.5 V, R L = 2 kω to GND; all specifications 4 C to +5 C, unless otherwise specified. SLS47 DECEMBER 23 SYMBOL PRMETER TEST CONDITIONS MIN TYP MX UNITS t FD Fall time of SD signal Standard mode 3 ns Fast mode 2 +.C B 3 ns High-speed mode, C B = pf max 8 ns High-speed mode, C B = 4 pf max 2 6 ns Standard mode 4. µs t SU ; t STO Setup time for STOP con- dition Fast mode 6 ns High-speed mode 6 ns Capacitive load for SD and C B 4 pf SCL Pulse width of spike supt SP pressed High-speed mode Fast mode 5 ns ns Noise margin at the HIGH Standard mode V NH level for each connected de- Fast mode.2 V DD V vice (including hysteresis) High-speed mode Noise margin at the LOW Standard mode V NL level for each connected de- Fast mode. V DD V vice (including hysteresis) High-speed mode LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE Channel B = 5 V DD Figure. Figure 2. 5
SLS47 DECEMBER 23 TYPICL CHRCTERISTICS (continued) t T = +25 C, unless otherwise noted. LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LE LSB.5.5 Channel C V DD = 5 V LE LSB.5.5 Channel D V DD = 5 V.5.5 DLE LSB.25.25 DLE LSB.25.25.5 32 64 96 28 6 92 224 Digital Input Code 255.5 32 64 96 28 6 92 224 Digital Input Code 255 Figure 3. Figure 4. LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LE LSB.5.5 Channel V DD = 2.7 V LE LSB.5.5 Channel B V DD = 2.7 V.5.5 DLE LSB.25.25 DLE LSB.25.25.5 32 64 96 28 6 92 224 Digital Input Code 255.5 32 64 96 28 6 92 224 Digital Input Code 255 Figure 5. Figure 6. LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LINERITY ERROR ND DIFFERENTIL LINERITY ERROR vs DIGITL INPUT CODE LE LSB.5.5 Channel C V DD = 2.7 V LE LSB.5.5 Channel D V DD = 2.7 V.5.5 DLE LSB.25.25 DLE LSB.25.25.5 32 64 96 28 6 92 224 Digital Input Code 255.5 32 64 96 28 6 92 224 Digital Input Code 255 Figure 7. Figure 8. 6
TYPICL CHRCTERISTICS (continued) t T = +25 C, unless otherwise noted. SLS47 DECEMBER 23 2 V DD = 5 V ZERO-SCLE ERROR vs TEMPERTURE 5 V DD = 2.7 V ZERO-SCLE ERROR vs TEMPERTURE Zero-Scale Error mv 5 CH C CH B CH D CH Zero-Scale Error mv 5 CH C CH B CH D CH 5 4 2 5 8 T Free ir Temperature C 4 2 5 8 T Free ir Temperature C Figure 9. Figure. Full-Scale Error mv 3 25 2 5 5 FULL-SCLE ERROR vs TEMPERTURE V DD = 5 V CH C CH CH D CH B Full-Scale Error mv 2 5 5 FULL-SCLE ERROR vs TEMPERTURE V DD = 2.7 V CH C CH CH D CH B 4 2 5 8 T Free ir Temperature C 4 2 5 8 T Free ir Temperature C Figure. Figure 2. V OUT Output Voltage V.5.25..75.5.25. SINK CURRENT CPBILITY T NEGTIVE RIL Typical For ll Channels V DD = 2.7 V V DD = 5.5 V DC Loaded With H 2 3 4 5 I SINK Sink Current m V OUT Output Voltage V 5.5 5.45 5.4 5.35 5.3 SOURCE CURRENT CPBILITY T POSITIVE RIL DC Loaded With FF H V DD = 5.5 V Typical For ll Channels 2 3 4 5 I SOURCE Source Current m Figure 3. Figure 4. 7
SLS47 DECEMBER 23 TYPICL CHRCTERISTICS (continued) t T = +25 C, unless otherwise noted. SOURCE CURRENT CPBILITY T POSITIVE RIL SUPPLY CURRENT vs DIGITL INPUT CODE V OUT Output Voltage V 2.7 2.6 2.5 2.4 2.3 DC Loaded With FF H V DD = 2.7 V Typical For ll Channels 2 3 4 5 I SOURCE Source Current m I DD Supply Current µ 8 7 6 5 4 3 2 V DD = 5.5 V V DD = 2.7 V ll Channels Powered, No Load 32 64 96 28 6 92 224 Digital Input Code 255 Figure 5. Figure 6. SUPPLY CURRENT vs TEMPERTURE SUPPLY CURRENT vs SUPPLY VOLTGE 7 7 I DD Supply Current µ 6 V DD = 5.5 V 5 4 V DD = 2.7 V 3 2 ll Channels Powered, No Load 4 2 5 8 I DD Supply Current µ 65 6 55 5 45 4 35 3 25 ll DCs Powered, No Load 2 2.7 3. 3.5 3.9 4.3 4.7 5. 5.5 T Free ir Temperature C V DD Supply Voltage V Figure 7. Figure 8. I DD Supply Current µ 2 8 6 4 SUPPLY CURRENT vs LOGIC INPUT VOLTGE T = 25 C Input (ll Other Inputs = GND) V DD = 5.5 V Frequency 2 5 5 HISTOGRM OF CURRENT CONSUMPTION V DD = 5 V V DD = 2.7 V 2 2 3 4 5 5 52 54 56 58 6 62 64 66 68 7 72 74 V Logic Logic Input Voltage V I DD Current Consumption µ Figure 9. Figure 2. 8
TYPICL CHRCTERISTICS (continued) t T = +25 C, unless otherwise noted. SLS47 DECEMBER 23 Frequency 2 5 5 HISTOGRM OF CURRENT CONSUMPTION V DD = 2.7 V V OUT Output Voltage V 6 5 4 3 2 EXITING POWER-DOWN MODE V DD = 5 V Powerup to Code 25 4 42 44 46 48 5 52 54 56 58 6 62 I DD Current Consumption µ Time (2 µs/div) Figure 2. Figure 22. 5 LRGE SIGNL SETTLING TIME 3. LRGE SIGNL SETTLING TIME V OUT Output Voltage V 4 3 2 V DD = 5 V Output Loaded with 2 pf to GND % to 9% FSR V OUT Output Voltage V 2.5 2..5..5 V DD = 2.7 V Output Loaded with 2 pf to GND % to 9% FSR. Time (25 µs/div) Time (25 µs/div) Figure 23. Figure 24. Output Error (mv) 24 2 6 2 8 4 BSOLUTE ERROR BSOLUTE ERROR V DD = 5 V, T = 25 C Channel Output Channel C Output Channel B Output Channel D Output Output Error (mv) 8 V DD = 2.7 V, T = 25 C 4 Channel D Output Channel Output 6 2 Channel B Output 2 Channel C Output 32 64 96 28 6 92 224 Digital Input Code 255 6 32 64 96 28 6 92 224 255 Digital Input Code Figure 25. Figure 26. bsolute error is the deviation from ideal DC characteristics. It includes affects of offset, gain, and integral linearity. 9
_ THEORY OF OPERTION D/ SECTION 5 k Ref Resistor String + Ref+ DD V TUO V GND GND mplifier Output o T R R R R 5 k - 7 k DD V DC Register D 652 DD V TUO V SLS47 DECEMBER 23 The architecture of the consists of a string DC followed by an output buffer amplifier. Figure 27 shows a generalized block diagram of the DC architecture. Figure 27. R-String DC rchitecture The input coding to the is unsigned binary, which gives the ideal output voltage as: Where D = decimal equivalent of the binary code that is loaded to the DC register; it can range from to 255. RESISTOR STRING The resistor string section is shown in Figure 28. It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Because the architecture consists of a string of resistors, it is specified monotonic. Figure 28. Typical Resistor String Output mplifier The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output, which gives an output range of V to V DD. It is capable of driving a load of 2 kω in parallel with pf to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is V/µs with a half-scale settling time of 6µs with the output unloaded. I 2 C Interface I 2 C is a 2-wire serial interface developed by Philips Semiconductor (see I 2 C-Bus Specification, Version 2., January 2). The bus consists of a data line (SD) and a clock line (SCL) with pullup structures. When the bus is idle, both SD and SCL lines are pulled high. ll the I 2 C compatible devices connect to the I 2 C bus through open drain I/O pins, SD and SCL. master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the STRT and STOP of data transfer. slave device receives and/or transmits data on the bus under control of the master device.
SCL SD P Stop Condition S Start Condition SCL SD SLS47 DECEMBER 23 THEORY OF OPERTION (continued) The works as a slave and supports the following data transfer modes, as defined in the I 2 C-Bus Specification: standard mode ( kbps), fast mode (4 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode. The supports 7-bit addressing; -bit addressing and general call address are not supported. F/S-Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SD line while SCL is high, as shown in Figure 29. ll I 2 C-compatible devices should recognize a start condition. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SD line. During all transmissions, the master ensures that data is valid. valid data condition requires the SD line to be stable during the entire high period of the clock pulse (see Figure 3). ll devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 3) by pulling the SD line low during the entire high period of the 9 th SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit ) or receive data from the slave (R/W bit ). In either case, the receiver needs to acknowledge the data sent by the transmitter. So acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and -bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SD line from low to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link with the addressed slave. ll I 2 C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. H/S-Mode Protocol When the bus is idle, both SD and SCL lines are pulled high by the pullup devices. The master generates a start condition followed by a valid serial byte containing H/S master code XXX. This transmission is made in F/S-mode at no more than 4 Kbps. No device is allowed to acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). fter this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. stop condition ends the H/S-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in H/S-mode. Figure 29. STRT and STOP Conditions
SLS47 DECEMBER 23 THEORY OF OPERTION (continued) SD SCL Data Line Stable; Data Valid Change of Data llowed Figure 3. Bit Transfer on the I 2 C Bus Data Output by Transmitter Not cknowledge Data Output by Receiver cknowledge SCL From Master S STRT Condition 2 8 9 Figure 3. cknowledge on the I 2 C Bus Clock Pulse for cknowledgement Recognize STRT or REPETED STRT Condition Generate CKNOWLEDGE Signal Recognize STOP or REPETED STRT Condition P SD MSB ddress cknowledgement Signal From Slave Sr R/W SCL S or Sr STRT or Repeated STRT Condition 2 7 8 9 CK Clock Line Held Low While Interrupts are Serviced Figure 32. Bus Protocol 2 3-8 9 CK Sr or P STOP or Repeated STRT Condition 2
I 2 C Update Sequence ddress Byte Broadcast ddress Byte SLS47 DECEMBER 23 The requires a start condition, a valid I 2 C address, a control byte, an MSB byte, and an LSB byte for a single update. fter the receipt of each byte, acknowledges by pulling the SD line low during the high period of a single clock pulse. valid I 2 C address selects the. The control byte sets the operational mode of the selected. Once the operational mode is selected by the control byte, expects an MSB byte followed by an LSB byte for data update to occur. performs an update on the falling edge of the acknowledge signal that follows the LSB byte. Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte continuously determine the type of update performed. Thus, for the first update, requires a start condition, a valid I 2 C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates, needs an MSB byte and an LSB byte as long as the control command remains the same. Using the I 2 C high-speed mode (f scl = 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DC update other than the first update can be done within 8 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 88.88 KSPS. Using the fast mode (f scl = 4 khz), clock running at 4 khz, maximum DC update rate is limited to 22.22 KSPS. Once a stop condition is received releases the I 2 C bus and awaits a new start condition. MSB LSB R/W The address byte is the first byte received following the STRT condition from the master device. The first five bits (MSBs) of the address are factory preset to. The next two bits of the address are the device select bits and. The, address inputs can be connected to V DD or digital GND, or can be actively driven by TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of the. Up to 4 devices () can still be connected to the same I 2 C-Bus. MSB LSB Broadcast addressing is also supported by. Broadcast addressing can be used for synchronously updating or powering down multiple devices. is designed to work with other members of the DC857x and DC757x families to support multichannel synchronous update. Using the broadcast address, responds regardless of the states of the address pins. Broadcast is supported only in write mode (Master writes to ). 3
SLS47 DECEMBER 23 Control Byte MSB LSB L L X Sel Sel PD Table. Control Register Bit Descriptions Bit Name L L2 Sel Sel PD Bit Number/Description Load (Mode Select) Bit Load (Mode Select) Bit Buff Sel Bit Buff Sel Bit re used for selecting the update mode. Store I 2 C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register of a selected channel. This mode does not change the DC output of the selected channel. Update selected DC with I 2 C data. Most commonly utilized mode. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register and in the DC register of the selected channel. This mode changes the DC output of the selected channel with the new data. 4-Channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register and in the DC register of the selected channel. Simultaneously, the other three channels get updated with previously stored data from the temporary register. This mode updates all four channels together. Broadcast update mode. This mode has two functions. In broadcast mode, responds regardless of local address matching, and channel selection becomes irrelevant as all channels update. This mode is intended to enable up to 6 channels simultaneous update, if used with the I 2 C broadcast address ( ). If Sel= If Sel= Channel Channel B Channel C Channel D Power Down Flag Normal operation ll four channels are updated with the contents of their temporary register data. ll four channels are updated with the MS-BYTE and LS-BYTE data or powerdown. Channel Select Bits Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2). 4
Table 2. Control Byte C7 C6 C5 C4 C3 C2 C C MSB7 MSB6 MSB5... SLS47 DECEMBER 23 Don't MSB MSB- MSB-2 Load Load Ch Sel Ch Sel PD Care (PD) (PD2)...LSB DESCRIPTION (ddress Select) Write to temporary X Data register (TR) with data Write to temporary X Data register B (TRB) with data Write to temporary X Data register C (TRC) with data Write to temporary X Data register D (TRD) with data (,,, or ) Write to TRx (selected X see Table 8 by C2 &C w/powerdown Command (,,, or ) Write to TRx (selected X Data by C2 &C and load DCx w/data (,,, or ) Power-down DCx X see Table 8 (selected by C2 and C) (,,, or ) Write to TRx (selected X Data by C2 &C w/ data and load all DCs (,,, or ) Power-down DCx X see Table 8 (selected by C2 and C) & load all DCs Broadcast Modes (controls up to 4 devices on a single serial bus) Update all DCs, all X X X X X X devices with previously stored TRx data Update all DCs, all X X X X Data devices with MSB[7:] and LSB[7:] data X X X X see Table 8 Power-down all DCs, all devices Most Significant Byte Most significant byte MSB[7:] consists of eight most significant bits of 8-bit unsigned binary D/ conversion data. If C=, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8. Least Significant Byte Least significant byte LSB[7:] consists of 8 don't care bits. updates at the falling edge of the acknowledge signal that follows the LSB[] bit. Therefore, LSB [7:] is needed for the update to occur. Default Readback Condition If the user initiates a readback of a specified channel without first writing data to that specified channel, the default readback is all zeros, since the readback register is initialized to during the power on reset phase. 5
S SL Registers as a Slave Receiver - Standard and Fast Mode C ddress Pin Pin ddress C = I I = LSB Factory Preset OP Condition RT Condition Repeated ST Not cknowledge (SD HIG cknowledge (SD LOW) From to Master ransferred ord = 6 Bit cknowledge) + ords VE DDRESS 2 2 = Read from to rite W = R/W P / C-SL VE DDRESS: 2 W LS-Byte MSB (n* W T Data I MS-Byte Ctrl-Byte R/W = RT Condition ST= (write) ST= = = P Sr S From Master to SLS47 DECEMBER 23 Table 3. rchitecture Register Descriptions REGISTER CTRL[7:] MSB[7:] TR[9:], TRB[9:], TRC[9:], TRD[9:] DR[9:], DRB[9:], DRC[9:], DRD[9:] DESCRIPTION Stores 8-bit wide control byte sent by the master Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data. -bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 8 LSBs store data. -bit DC registers for each channel. Two MSBs store power-down information, 8 LSBs store DC data. n update of this register means a DC update with data or power down. Figure 33 shows the standard and fast mode master transmitter addressing a Slave Receiver with a 7-bit address. Figure 33. Standard and Fast Mode: Slave Receiver 6
as a Slave Receiver - High-Speed Mode 2 Power Down Flag Buff Sel (Channel) Select Bit Bit Select (Channel) Sel Buff Load (Mode Select) Bit Bit Select) (Mode Load Extended ddress Bit Bit ddress Extended 3 PD Sel Sel LS-Byte: MS-Byte: ransferred ord = 6 Bit cknowledge) + ords Slave ddress HS-Master Code Slave ddress Sr HS-Mode Continues P F/S-Mode PD LSB Sel2 / Sel X W LS-Byte L L (n* W T Data = MS-Byte = = = = = = X = Don t Care L L 2 3 MSB Control Byte: Ctrl-Byte HS-Mode R/W X LSB D LSB R/W X LSB (write) X D X D2 X Sr X D3 X D4 X D5 X D6 X D7 S F/S-Mode D = Data Bits D MSB MSB MSB HS-Mode Master Cod SLS47 DECEMBER 23 Figure 34 shows the high-speed mode master transmitter addressing a Slave Receiver with a 7-bit address. Figure 34. High-Speed Mode: Slave Receiver 7
SLS47 DECEMBER 23 Master Transmitter Writing to a Slave Receiver () in Standard/Fast Modes ll write access sequences begin with the device address (with R/W = ) followed by the control byte. This control byte specifies the operation mode of and determines which channel of is being accessed in the subsequent read/write operation. The LSB of the control byte (PD-Bit) determines if the following data is power-down data or regular data. With (PD-Bit = ) the expects to receive data in the following sequence HIGH-BYTE LOW-BYTE HIGH-BYTE LOW-BYTE..., until a STOP Condition or REPETED STRT Condition on the I 2 C-Bus is recognized (refer to the DT INPUT MODE section of Table 4). With (PD-Bit = ) the expects to receive 2 Bytes of power-down data (refer to the POWER DOWN MODE section of Table 4). DT INPUT MODE Table 4. Write Sequence in F/S Mode Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master R/W Write addressing (R/W=) cknowledges Master Load Load x Buff Sel Buff Sel PD Control byte (PD=) cknowledges Master D7 D6 D5 D4 D3 D2 D D Writing data word, high byte cknowledges Master x x x x x x x x Writing data word, low byte cknowledges Master Data or Stop or Repeated Start () Data or done (2) POWER DOWN MODE Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master R/W Write addressing (R/W=) cknowledges Master Load Load x Buff Sel Buff Sel PD Control byte (PD = ) cknowledges Master PD PD2 Writing data word, high byte cknowledges Master x x x x x x x x Writing data word, low byte cknowledges Master Stop or Repeated Start () Done () Use repeated STRT to secure bus operation and loop back to the stage of write addressing for next Write. (2) Once is properly addressed and control byte is sent, HIGH BYTE LOW BYTE sequences can repeat until a STOP condition or repeated STRT condition is received. 8
Master Transmitter Writing to a Slave Receiver () in HS Mode SLS47 DECEMBER 23 When writing data to the in HS-mode, the master begins to transmit what is called the HS-Master Code ( XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge. The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with R/W = ) after which the acknowledges by pulling SD low. This address byte is usually followed by the control byte, which is also acknowledged by the. The LSB of the control byte (PD-Bit) determines if the following data is power-down data or regular data. With (PD-Bit = ) the expects to receive data in the following sequence HIGH-BYTE LOW-BYTE HIGH-BYTE LOW-BYTE..., until a STOP condition or repeated start condition on the I 2 C-Bus is recognized (refer to Table 5 HS-MODE WRITE SEQUENCE - DT). With (PD-Bit = ) the expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE WRITE SEQUENCE - POWER DOWN). Table 5. Master Transmitter Writes to Slave Receiver () in HS-Mode HS MODE WRITE SEQUENCE - DT Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master X X X HS Mode Master Code NONE Master Not cknowledge Repeated Start No device may acknowledge HS master code Master R/W Write addressing (R/W=) cknowledges Master Load Load Buff Sel Buff Sel PD Control byte (PD=) cknowledges Master D7 D6 D5 D4 D3 D2 D D Writing data word, MSB cknowledges Master x x x x x x x x Writing data word, LSB cknowledges Master Data or Stop or Repeated Start () Data or done (2) HS MODE WRITE SEQUENCE - POWER DOWN Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master X X X HS Mode Master Code NONE Master Not cknowledge Repeated Start No device may acknowledge HS master code Master R/W Write addressing (R/W = ) cknowledges Master Load Load 2 Buff Sel Buff Sel PD Control Byte (PD=) cknowledges Master PD PD2 Writing data word, high byte cknowledges Master x x x x x x x x Writing data word, low byte cknowledges Master Stop or repeated start () Done () Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. (2) Once is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start condition is received. 9
S SL as a Slave Transmitter - Standard and Fast Mode LS-Byte MS-Byte PDN-Byte P PD Slave ddress MS-Byte Slave ddress VE DDRESS P (MSTER) (3 Bytes + cknowledge) (read) ransferred T Data (MSTER) (2 Bytes + cknowledge) ransferred T Data LS-Byte (MSTER) (MSTER) (MSTER) R/W () (read) R/W () Sr Sr LSB PD () Ctrl <7:> R/W R/W (write) PD2 = (Normal Mode) () Slave ddress PD MSB = (Power Down Flag) PD = Power Down B PD2 = Power Down B PDN-Byte: as a Slave Transmitter - High-Speed Mode LS-Byte MS-Byte PDN-Byte P PD Slave ddress MS-Byte Slave ddresspd Sr Ctrl <7:> F/S-Mode P (MSTER) (3 Bytes + cknowledge) ransferred T Data (MSTER) (2 Bytes + cknowledge) ransferred T Data LS-Byte (MSTER) (MSTER) (MSTER) R/W (read) R/W (read) () () Sr Sr HS-Mode () = (Normal Mode) (write) () = (Power Down Flag) S HS-Master Code SLS47 DECEMBER 23 Figure 35 shows the standard and fast mode master transmitter addressing a Slave Transmitter with a 7-bit address. Figure 35. Standard and Fast Mode: Slave Transmitter Figure 36 shows an I 2 C-Master addressing in high-speed mode (with a 7-bit address), as a Slave Transmitter. Figure 36. High-Speed Mode: Slave Transmitter 2
Master Receiver Reading From a Slave Transmitter () in Standard/Fast Modes SLS47 DECEMBER 23 When reading data back from the, the user begins with an address byte (with R/W = ) after which the will acknowledge by pulling SD low. This address byte is usually followed by the Control Byte, which is also acknowledged by the. Following this there is a REPETED STRT condition by the Master and the address is resent with (R/W = ). This is acknowledged by the, indicating that it is prepared to transmit data. Two or three bytes of data are then read back from the, depending on the (PD-Bit). The value of Buff-Sel and Buff-Sel determines, which channel data is read back. STOP Condition follows. With the (PD-Bit = ) the transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 2 bytes). With the (PD-Bit = ) the transmits 3 bytes of data, POWER-DOWN-BYTE followed by the HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes). DT REDBCK MODE - 2 BYTES Table 6. Read Sequence in F/S Mode Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master R/W Write addressing (R/W=) cknowledges Master Load Load x Buff Sel Buff Sel PD Control byte (PD=) Master cknowledges Repeated Start Master R/W Read addressing (R/W = ) cknowledges D7 D6 D5 D4 D3 D2 D D Reading data word, high byte Master Master cknowledges x x x x x x x x Reading data word, low byte Master Master Not cknowledges Master signal end of read Master Stop or Repeated Start () Done DT REDBCK MODE - 3 BYTES Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master R/W Write addressing (R/W=) cknowledges Master Load Load x Buff Sel Buff Sel PD Control byte (PD=) Master cknowledges Repeated Start Master R/W Read addressing (R/W = ) cknowledges PD PD2 Read power down byte Master Master cknowledges D7 D6 D5 D4 D3 D2 D D Reading data word, high byte Master Master cknowledges x x x x x x x x Reading data word, low byte Master Master Not cknowledges Master signal end of read Master Stop or Repeated Start () Done () Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. 2
SLS47 DECEMBER 23 Master Receiver Reading From a Slave Transmitter () in HS-Mode Power-On Reset Power-Down Modes When reading data to the in HS-MODE, the master begins to transmit, what is called the HS-Master Code ( XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge. The Master then switches to HS-mode and issues a REPETED STRT condition, followed by the address byte (with R/W = ) after which the acknowledges by pulling SD low. This address byte is usually followed by the control byte, which is also acknowledged by the. Then there is a REPETED STRT condition initiated by the master and the address is resent with (R/W = ). This is acknowledged by the, indicating that it is prepared to transmit data. Two or Three bytes of data are then read back from the, depending on the (PD-Bit). The value of Buff-Sel and Buff-Sel determines, which channel data is read back. STOP condition follows. With the (PD-Bit = ) the transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence). With the (PD-Bit = ) the transmits 3 bytes of data, POWER-DOWN-BYTE followed by the HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence). HS MODE REDBCK SEQUENCE Table 7. Master Receiver Reading Slave Transmitter () in HS-Mode Transmitter MSB 6 5 4 3 2 LSB Comment Master Start Begin sequence Master X X X HS Mode Master Code NONE Master Not cknowledge Repeated Start No device may acknowledge HS master code Master R/W Write addressing (R/W=) cknowledges Master Load Load X Buff Sel Buff Sel PD Control byte (PD = ) Master cknowledges Repeated Start Master R/W Read addressing (R/W=) cknowledges PD PD2 Power-down byte Master Master cknowledges D7 D6 D5 D4 D3 D2 D D Reading data word, high byte Master Master cknowledges x x x x x x x x Reading data word, low byte Master Master Not cknowledges Master signal end of read Master Stop or Repeated Start Done The contains a power-on-reset circuit that controls the output voltage during power up. On power up, the DC register is filled with zeros and the output voltage is V; it remains there until a valid write sequence is made to the DC. This is useful in applications where it is important to know the state of the output of the DC while it is in the process of powering up. No device pin should be brought high before supply is applied. The contains four separate power-down modes of operation. The modes are programmable via two most significant bits of the MSB byte, while (CTRL[] = PD = ). Table 8 shows how the state of these bits correspond to the mode of operation of the device. 22
Table 8. Power-Down Modes of Operation for the CTRL[] MSB[7] MSB[6] OPERTING MODE High Impedance Output kω to GND kω to GND High Impedance SLS47 DECEMBER 23 When (CTRL[] = PD = ), the device works normally with its normal power consumption of 5 µ at 5 V per channel. However, for the power-down modes, the supply current falls to 2 n at 5 V (5 n at 3 V). Not only does the supply current fall but also the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to GND through a -kω resistor, a -kω resistor or left open-circuit (high impedance). The output stage is illustrated in Figure 37. Resistor String DC mplifier V OUT Powerdown Circuitry Resistor Network CURRENT CONSUMPTION DRIVING RESISTIVE ND CPCITIVE LODS Figure 37. Output Stage During Power Down ll linear circuitry is shut down when the power-down mode is activated. However, the contents of the DC register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for V DD = 5 V and 5 µs for V DD = 3 V. (See the Typical Curves section for additional information.) The offers a flexible power-down interface based on channel register operation. channel consists of a single 8-bit DC with power-down circuitry, a temporary storage register (TR) and a DC register (DR). TR and DR are both bits wide. Two MSBs represent the power-down condition and the 8 LSBs represent data for TR and DR. By using bits 9 and 8 of TR and DR, a power-down condition can be temporarily stored and used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[9] and TR[8] (DR[9] and DR[8]) when the power-down flag (CTRL[] = PD) is set. Therefore, treats power-down conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a power-down condition to all the s in the system, or it is possible to simultaneously power down a channel while updating data on other channels. The typically consumes 5µ at V DD = 5 V and 25µ at V DD = 3 V for each active channel, including reference current consumption. dditional current consumption can occur at the digital inputs if V IH << V DD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DC. In power-down mode, typical current consumption is 2 n. The output stage is capable of driving loads of up to pf while remaining stable. Within the offset and gain error margins, the can operate rail-to-rail when driving a capacitive load. Resistive loads of 2 kω can be driven by the while achieving a good load regulation. When the outputs of the DC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-B output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DC. This only occurs within approximately the top 2 mv of the DC's digital input-to-voltage output transfer characteristic. 23
SLS47 DECEMBER 23 CROSSTLK OUTPUT VOLTGE STBILITY SETTLING TIME ND OUTPUT GLITCH PERFORMNCE The architecture uses separate resistor strings for each DC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel is typically less than.25 LSBs. The ac crosstalk measured (for a full-scale, khz sine wave output generated at one channel, and measured at the remaining output channel) is typically under db. The exhibits excellent temperature stability of ±3 ppm/ C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µv window for a ± C ambient temperature change. Combined with good dc noise performance and true 8-bit differential linearity, the becomes a perfect choice for closed-loop control applications. Settling time to within the 8-bit accurate range of the is achievable within 6 µs for a full-scale code change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The high-speed serial interface of the is designed in order to support up to 88 ksps update rate. For full-scale output swings, the output stage of each channel typically exhibits less than mv of overshoot and undershoot when driving a 2 pf capacitive load. Code-to-code change glitches are extremely low (~ µv) given that the code-to-code transition does not cross an Nx6 code boundary. Due to internal segmentation of the, code-to-code glitches occur at each crossing of an Nx6 code boundary. These glitches can approach mvs for N = 5, but settle out within ~2 µs. Sufficient bypass capacitance is required to ensure µs settling under capacitive loading. To observe the settling performance under resistive load conditions, the power supply (hence reference supply) must settle quicker than the. 24
6 7 8 9 5 4 3 2 PPLICTION INFORMTION BSIC CONNNECTIONS to k I C Pullup Resistors 2 GND DD V SCL SD D TUO V C TUO V B TUO V TUO V C Inputs., except I DD V (typical) Ω Ω SD SCL k I C Port 2 NOTE: power and inpu Microcontroller or Microprocessor With SLS47 DECEMBER 23 The following sections give example circuits and tips for using the in various applications. For more information, contact your local TI representative, or visit the Texas Instruments website at http://. For many applications, connecting the is extremely simple. basic connection diagram for the is shown in Figure 38. The. µf bypass capacitors help provide the momentary bursts of extra current needed from the supplies. USING GPIO PORTS FOR I 2 C Figure 38. Typical Connections The interfaces directly to standard mode, fast mode and high-speed mode I 2 C controllers. ny microcontroller's I 2 C peripheral, including master-only and non-multiple-master I 2 C peripherals, work with the. The does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not necessary to provide for this unless other devices are on the same I 2 C bus. Pullup resistors are necessary on both the SD and SCL lines because I 2 C bus drivers are open-drain. The size of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus drivers may not be able to pull the bus line low. Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or outputs. If an I 2 C controller is not available, the can be connected to GPIO pins, and the I 2 C bus protocol simulated, or bit-banged, in software. n example of this for a single is shown in Figure 39. 25
SLS47 DECEMBER 23 PPLICTION INFORMTION (continued) V OUT 2 V OUT B 9 3 GND V DD 8 V DD 4 V OUT C SD 7 5 V OUT D SCL 6 Microcontroller or Microprocessor GPIO- GPIO-2 NOTE: power and input/output connections are omitted for clarity, except I C Inputs. POWER SUPPLY REJECTION Figure 39. Using GPIO With a Single Bit-banging I 2 C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is pulling the line low, this reads as a zero in the port's input register. Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this because the never drives its clock line low. This technique can also be used with multiple devices, and has the advantage of lower current consumption due to the absence of a resistive pullup. If there are any devices on the bus that may drive their clock lines low, the above method should not be used. The SCL line should be high-z or zero, and a pullup resistor provided as usual. Note also that this cannot be done on the SD line in any case, because the drives the SD line low from time to time, as all I 2 C devices do. Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some microcontrollers, but usually these are too weak for I 2 C communication. Test any circuit before committing it to production. The positive reference voltage input of is internally tied to the power supply pin of the device. This increases I 2 C system flexibility, creating room for an extra I 2 C address pin in a low pin-count package. To eliminate the supply noise appearing at the DC output, the user must pay close attention to how is powered. The supply to must be clean and well regulated. For best performance, use of a precision voltage reference is recommended to supply power to. This is equivalent to providing a precision 26
REF2 USING REF2 S POWER SUPPLY FOR V D SCL D 5 V T= V to 5 V UO.6 m 5 V SD I C 2 Interface PPLICTION INFORMTION (continued) SLS47 DECEMBER 23 external reference to the device. Due to low power consumption of, load regulation errors are negligible. In order to avoid excess power consumption at the Schmitt-triggered inputs of, the precision reference voltage should be close to the I 2 C bus pullup voltage. For 3-V, 3.3-V and 5-V I 2 C bus pullup voltages, REF293, REF2933 and REF2 precision voltage references are recommended respectively. These precision voltage references can be used to supply power for multiple devices on a system. Due to the extremely low supply current required by the, a possible configuration is to use a REF2 +5 V precision voltage reference to supply the required voltage to the 's supply input as well as the reference input, as shown in Figure 4. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF2 outputs a steady supply voltage for the. If the REF2 is used, the current it needs to supply to the is 6 µ typical and 9 µ max for V DD = 5 V. When a DC output is loaded, the REF2 also needs to supply the current to the load. The total typical current required (with a 5-kΩ load on a single DC output) is: 6 µ + (5 V / 5 kω) =.6 m The load regulation of the REF2 is typically.5%/m, which results in an error of 4µV for.6-m of current drawn from it. This corresponds to a.2 LSB error for a V to 5 V output range. Figure 4. REF2 Power Supply LYOUT precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The power applied to V DD should be well-regulated and low noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DC output voltage through various paths between the power connections and analog output. s with the GND connection, V DD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a -µf to -µf capacitor in parallel with a.-µf bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a -µf electrolytic capacitor or even a Pi filter made up of inductors and capacitors all designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise. 27