Power MOSFET PRODUCT SUMMARY (V) 400 R DS(on) (Ω) = 0.55 Q g (Max.) (nc) 63 Q gs (nc) 9.0 Q gd (nc) 3 Configuration Single FEATURES Dynamic dv/dt Rating Repetitive Avalanche Rated Fast Switching Ease of Paralleling Simple Drive Requirements Lead (Pb)free Available Available RoHS* COMPLIANT TO0 G DS G D S NChannel MOSFET DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low onresistance and costeffectiveness. The TO0 package is universally preferred for all commercialindustrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO0 contribute to its wide acceptance throughout the industry. ORDERING INFORMATION Package Lead (Pb)free SnPb TO0 IRF740PbF SiHF740E3 IRF740 SiHF740 ABSOLUTE MAXIMUM RATINGS T C = 5 C, unless otherwise noted PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 400 V GateSource Voltage ± 0 Continuous Drain Current at T C = 5 C 10 T C = 100 C 6.3 A Pulsed Drain Current a M 40 Linear Derating Factor 1.0 W/ C Single Pulse Avalanche Energy b E AS 50 mj Repetitive Avalanche Current a I AR 10 A Repetitive Avalanche Energy a E AR 13 mj Maximum Power Dissipation T C = 5 C P D 15 W Peak Diode Recovery dv/dt c dv/dt 4.0 V/ns Operating Junction and Storage Temperature Range T J, T stg 55 to 150 Soldering Recommendations (Peak Temperature) for 10 s 300 d C Mounting Torque 63 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. V DD = 50 V, starting T J = 5 C, L = 9.1 mh, R G = 5 Ω, I AS = 10 A (see fig. 1). c. I SD 10 A, di/dt 10 A/µs, V DD, T J 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply 10 lbf in 1.1 N m Document Number: 91054 www.vishay.com S8191Rev. A, 16Jun08 1
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 6 CasetoSink, Flat, Greased Surface R thcs 0.50 C/W Maximum JunctiontoCase (Drain) R thjc 1.0 SPECIFICATIONS T J = 5 C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage = 0 V, = 50 µa 400 V Temperature Coefficient Δ /T J Reference to 5 C, = 1 ma 0.49 V/ C GateSource Threshold Voltage (th) =, = 50 µa.0 4.0 V GateSource Leakage I GSS = ± 0 V ± 100 na = 400 V, = 0 V 5 Zero Gate Voltage Drain Current SS = 30 V, = 0 V, T J = 15 C 50 µa DrainSource OnState Resistance R DS(on) = = 6.0 A b 0.55 Ω Forward Transconductance g fs = 50 V, = 6.0 A b 5.8 S Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance C iss C oss C rss = 0 V, = 5 V, f = 1.0 MHz, see fig. 5 1400 330 10 Total Gate Charge Q g 63 = 10 A, = 30 V, GateSource Charge Q gs = 9.0 see fig. 6 and 13 b GateDrain Charge Q gd 3 TurnOn Delay Time t d(on) 14 Rise Time t r V DD = 00 V, = 10 A 7 TurnOff Delay Time t d(off) R G = 9.1 Ω, R D = 0 Ω, see fig. 10 b 50 Fall Time t f 4 Between lead, Internal Drain Inductance L D 6 mm (0.5") from 4.5 D package and center of G Internal Source Inductance L S die contact 7.5 S DrainSource Body Diode Characteristics Continuous SourceDrain Diode Current I S MOSFET symbol 10 D Pulsed Diode Forward Current a I SM showing the integral reverse 40 G A p n junction diode S Body Diode Voltage V SD T J = 5 C, I S = 10 A, = 0 V b.0 V Body Diode Reverse Recovery Time t rr T J = 5 C, I F = 10 A, di/dt = 100 A/µs b 370 790 ns Body Diode Reverse Recovery Charge Q rr 3.8 8. µc Forward TurnOn Time t on Intrinsic turnon time is negligible (turnon is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 µs; duty cycle %. pf nc ns nh www.vishay.com Document Number: 91054 S8191Rev. A, 16Jun08
TYPICAL CHARACTERISTICS 5 C, unless otherwise noted 10 1 10 0 Top Bottom 15 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 4.5 V 10 1 10 0 150 C 5 C 10 1 10 0 10 1 0 µs Pulse Width T C = 5 C 10 1 4 0 µs Pulse Width = 50 V 5 6 7 8 9 10 91054_01, DraintoSource Voltage (V) 91054_03, GatetoSource Voltage (V) Fig. 1 Typical Output Characteristics, T C = 5 C Fig. 3 Typical Transfer Characteristics 91054_0 10 1 10 0 Top Bottom 15 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 10 1 10 0 10 1 4.5 V 0 µs Pulse Width T C = 150 C, DraintoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 91054_04 3.0.5.0 1.5 1.0 0.5 = 10 A = 0.0 60 40 0 0 0 40 60 80 100 10 140 160 T J, Junction Temperature ( C) Fig. Typical Output Characteristics, T C = 150 C Fig. 4 Normalized OnResistance vs. Temperature Document Number: 91054 www.vishay.com S8191Rev. A, 16Jun08 3
Capacitance (pf) 91054_05 500 000 1500 1000 500 = 0 V, f = 1 MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd C iss 0 10 0 10 1 C oss C rss, DraintoSource Voltage (V) I SD, Reverse Drain Current (A) 91054_07 150 C 10 1 5 C 10 0 10 1 = 0 V 0.50 0.70 0.90 1.10 1.30 1.50 V SD, SourcetoDrain Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage Fig. 7 Typical SourceDrain Diode Forward Voltage, GatetoSource Voltage (V) 91054_06 0 16 1 8 4 = 10 A = 50 V = 100 V = 400 V For test circuit see figure 13 0 0 15 30 45 60 75 Q G, Total Gate Charge (nc) 91054_08 10 3 5 10 5 10 5 1 5 0.1 Operation in this area limited by R DS(on) T C = 5 C T J = 150 C Single Pulse, DraintoSource Voltage (V) 10 µs 100 µs 1 ms 10 ms 5 5 5 0.1 1 10 10 5 10 3 Fig. 6 Typical Gate Charge vs. DraintoSource Voltage Fig. 8 Maximum Safe Operating Area www.vishay.com Document Number: 91054 4 S8191Rev. A, 16Jun08
10 R D 8 6 4 R G Pulse width 1 µs Duty factor 0.1 % D.U.T. Fig. 10a Switching Time Test Circuit V DD 91054_09 0 5 50 75 100 15 150 T C, Case Temperature ( C) 90 % Fig. 9 Maximum Drain Current vs. Case Temperature 10 % t d(on) t r t d(off) t f Fig. 10b Switching Time Waveforms 10 Thermal Response (Z thjc ) 91054_11 1 0.1 10 0 0.5 0. 0.1 0.05 0.0 0.01 Single Pulse (Thermal Response) P DM t 1 t Notes: 1. Duty Factor, D = t 1 /t. Peak T j = P DM x Z thjc T C 10 5 10 4 10 3 10 0.1 1 10 t 1, Rectangular Pulse Duration (S) Fig. 11 Maximum Effective Transient Thermal Impedance, JunctiontoCase Vary t p to obtain required I AS R G L D.U.T I AS V DD t p V DD t p 0.01 Ω I AS Fig. 1a Unclamped Inductive Test Circuit Fig. 1b Unclamped Inductive Waveforms Document Number: 91054 www.vishay.com S8191Rev. A, 16Jun08 5
E AS, Single Pulse Energy (mj) 100 1000 800 600 400 00 Top Bottom 4.5 A 5.3 A 10 A V DD = 50 V 0 5 50 75 100 15 150 91054_1c Starting T J, Junction Temperature ( C) Fig. 1c Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q G 1 V 0. µf 50 kω 0.3 µf Q GS Q GD D.U.T. V DS V G Charge Fig. 13a Basic Gate Charge Waveform 3 ma Fig. 13b Gate Charge Test Circuit I G Current sampling resistors www.vishay.com Document Number: 91054 6 S8191Rev. A, 16Jun08
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by duty factor "D" D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period = * D.U.T. I SD waveform Reverse recovery current Reapplied voltage Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt Inductor current Body diode forward drop V DD Ripple 5 % I SD * = 5 V for logic level devices Fig. 14 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91054. Document Number: 91054 www.vishay.com S8191Rev. A, 16Jun08 7
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