FQD3P50 P-Channel QFET MOSFET - 500 V, -.1 A, 4.9 Ω Description This P-Channel enhancement mode power MOSFET is produced using ON Semiconductor s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength. These devices are suitable for switched mode power supplies, active power factor correction (PFC), and electronic lamp ballasts. Features -.1 A, - 500 V, R DS(on) = 4.9 Ω (Max.) @ = - 10 V, ID = - 1.05 A Low Gate Charge (Typ. 18 nc) Low Crss (Typ. 9.5 pf) 100% Avalanche Tested Absolute Maximum Ratings T C = 5 C unless otherwise noted Symbol Parameter FQD3P50 Unit S Drain-Source Voltage -500 V I D Drain Current - Continuous (T C = 5 C) -.1 A Thermal Characteristics - Continuous (T C = 100 C) -1.33 A I DM Drain Current - Pulsed (Note 1) -8.4 A S Gate-Source Voltage ± 30 V E AS Single Pulsed Avalanche Energy (Note ) 50 mj I AR Avalanche Current (Note 1) -.1 A E AR Repetitive Avalanche Energy (Note 1) 5.0 mj dv/dt Peak Diode Recovery dv/dt (Note 3) -4.5 V/ns P D Power Dissipation (T A = 5 C) *.5 W Power Dissipation (T C = 5 C) 50 W - Derate above 5 C 0.4 W/ C T J, T STG Operating and Storage Temperature Range -55 to +150 C T L G D-PAK (TO5) Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 300 C Symbol Parameter FQD3P50 Unit R θjc Thermal Resistance, Junction-to-Case, Max..5 C/W R θja Thermal Resistance, Junction-to-Ambient, Max. * 50 C/W R θja Thermal Resistance, Junction-to-Ambient, Max. 110 C/W * When mounted on the minimum pad size recommended (PCB Mount) S D G! S!! D 009Semiconductor Components Industries, LLC. October-017,Rev. Publication Order Number: FQD3P50/D
Elerical Characteristics T C = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Unit Off Characteristics BS Drain-Source Breakdown Voltage = 0 V, I D = -50 µa -500 -- -- V BS Breakdown Voltage Temperature / T J Coefficient I D = -50 µa, Referenced to 5 C -- 0.4 -- V/ C I DSS = -500 V, = 0 V -- -- -1 µa Zero Gate Voltage Drain Current = -400 V, T C = 15 C -- -- -10 µa I GSSF Gate-Body Leakage Current, Forward = -30 V, = 0 V -- -- -100 na I GSSR Gate-Body Leakage Current, Reverse = 30 V, = 0 V -- -- 100 na On Characteristics (th) Gate Threshold Voltage =, I D = -50 µa -3.0 -- -5.0 V R DS(on) Static Drain-Source V On-Resistance GS = -10 V, I D = -1.05 A -- 3.9 4.9 Ω g FS Forward Transconductance = -50 V, I D = -1.05 A --.1 -- S Dynamic Characteristics C iss Input Capacitance = -5 V, = 0 V, -- 510 660 pf C oss Output Capacitance f = 1.0 MHz -- 70 90 pf C rss Reverse Transfer Capacitance -- 9.5 1 pf Switching Characteristics t d(on) Turn-On Delay Time -- 1 35 ns = -50 V, I D = -.7 A, t r Turn-On Rise Time R G = 5 Ω -- 56 10 ns t d(off) Turn-Off Delay Time -- 35 80 ns t f Turn-Off Fall Time (Note 4) -- 45 100 ns Q g Total Gate Charge = -400 V, I D = -.7 A, -- 18 3 nc Q gs Gate-Source Charge = -10 V -- 3.6 -- nc Q gd Gate-Drain Charge (Note 4) -- 9. -- nc Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current -- -- -.1 A I SM Maximum Pulsed Drain-Source Diode Forward Current -- -- -8.4 A V SD Drain-Source Diode Forward Voltage = 0 V, I S = -.1 A -- -- -5.0 V t rr Reverse Recovery Time = 0 V, I S = -.7 A, -- 70 -- ns Q rr Reverse Recovery Charge di F / dt = 100 A/µs -- 1.5 -- µc Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature. L = 10mH, I AS = -.1A, = -50V, R G = 5 Ω, Starting T J = 5 C 3. I SD -.7A, di/dt 00A/µs, BS, Starting T J = 5 C 4. Essentially independent of operating temperature
Typical Characteristics 10 0 8 Top : -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -6.0 V Bottom : -5.5 V 10-10 0 10 1 -, Drain-Source Voltage [V] 1. 50μs Pulse Test. T C = 5 Figure 1. On-Region Characteristics 10 0 150 5-55 1. = -50V. 50μs Pulse Test 4 6 8 10 -, Gate-Source Voltage [V] Figure. Transfer Characteristics R DS(on) [Ω], Drain-Source On-Resistance 7 6 5 4 3 = - 0V = - 10V Note : T J = 5 0 4 6 8 -I D, Drain Current [A] -I DR, Reverse Drain Current [A] 10 0 150 5 1. = 0V. 50μs Pulse Test 0.0 0.5 1.0 1.5.0.5 3.0 -V SD, Source-Drain Voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 100 1000 C iss = C gs + C gd (C ds = shorted) C oss = C ds + C gd C rss = C gd 1 10 = -100V Capacitance [pf] 800 600 400 00 C iss C oss C rss 1. = 0 V. f = 1 MHz -, Gate-Source Voltage [V] 8 6 4 = -50V = -400V Note : I D = -.7 A 0 10 0 10 1, Drain-Source Voltage [V] 0 0 4 6 8 10 1 14 16 18 0 Q G, Total Gate Charge [nc] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics 3
Typical Characteristics (Continued) -BS, (Normalized) Drain-Source Breakdown Voltage 1. 1.1 1.0 0.9 0.8-100 -50 0 50 100 150 00 T J, Junction Temperature [ o C] 1. = 0 V. I D = -50 μa Figure 7. Breakdown Voltage Variation vs. Temperature R DS(ON), (Normalized) Drain-Source On-Resistance.5.0 1.5 1.0 0.5 0.0-100 -50 0 50 100 150 00.5 T J, Junction Temperature [ o C] 1. = -10 V. I D = -1.35 A Figure 8. On-Resistance Variation vs. Temperature 10 1 10 0 Operation in This Area is Limited by R DS(on) 1. T C = 5 o C. T J = 150 o C 3. Single Pulse 10-10 0 10 1 10 10 3 -, Drain-Source Voltage [V] DC 10 ms 1 ms 100 µs.0 1.5 1.0 0.5 0.0 5 50 75 100 15 150 T C, Case Temperature [ ] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature Z θ JC (t), Thermal Response D=0.5 10 0 N otes : 0. 1. Z θ JC (t) =.5 /W M ax.. D uty F actor, D =t 1 /t 0.1 3. T JM - T C = P DM * Z θ JC (t) 0.05 0.0 0.01 single pulse P DM t 1 t 10-10 -5 10-4 10-3 10-10 0 10 1 t 1, S quare W ave P ulse D uration [sec] Figure 11. Transient Thermal Response Curve 4
1V 00nF -3mA 50KΩ 300nF Gate Charge Test Circuit & Waveform Same Type as DUT DUT -10V Q gs Q g Q gd Charge Resistive Switching Test Circuit & Waveforms R L t on t off t d(on) t r t d(off) tf R G 10% -10V DUT 90% Unclamped Inductive Switching Test Circuit & Waveforms L 1 E AS = ---- LI AS BS -------------------- BS - I D t p Time R G I D (t) (t) -10V DUT I AS t p BS 5
Peak Diode Recovery dv/dt Test Circuit & Waveforms + DUT _ I SD Driver R G Compliment of DUT (N-Channel) L dv/dt controlled by RG I SD controlled by pulse period ( Driver ) Gate Pulse Width D = -------------------------- Gate Pulse Period 10V I SD ( DUT ) ( DUT ) Body Diode Reverse Current V SD I RM di/dt I FM, Body Diode Forward Current Body Diode Forward Voltage Drop Body Diode Recovery dv/dt 6
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 1951 E. 3nd Pkwy, Aurora, Colorado 80011 USA Phone: 303 675 175 or 800 344 3860 Toll Free USA/Canada Fax: 303 675 176 or 800 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com Semiconductor Components Industries, LLC N. American Technical Support: 800 8 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 41 33 790 910 Japan Customer Focus Center Phone: 81 3 5817 1050 ON Semiconductor Website: Order Literature: http:///orderlit For additional information, please contact your local Sales Representative