Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use Benefits l l l Very Low RDSon) at 4.5V V GS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current IRLR833 IRLU833 HEXFET Power MOSFET V DSS R DSon) max Qg 3V 4.5m: 33nC D-Pak IRLR833 PD - 9454A I-Pak IRLU833 Absolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 3 V V GS Gate-to-Source Voltage ± I D @ T C = 5 C Continuous Drain Current, V GS @ V 4f I D @ T C = C Continuous Drain Current, V GS @ V 99f A I DM Pulsed Drain Current c 56 P D @T C = 5 C Maximum Power Dissipation g 4 W P D @T C = C Maximum Power Dissipation g Linear Derating Factor.95 W C T J Operating Junction and -55 to 5 C T STG Storage Temperature Range Soldering Temperature, for seconds Mounting torque, 6-3 or M3 screw 3.6mm from case) lbfxin.nxm) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.5 R θja Junction-to-Ambient PCB Mount) g 5 CW R θja Junction-to-Ambient Notes through are on page www.irf.com 394
IRLRU833 Static @ T J = 5 C unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 3 V ΒV DSS T J Breakdown Voltage Temp. Coefficient 9 mv C R DSon) Static Drain-to-Source On-Resistance 3.6 4.5 mω 4.4 5.5 V GS = 4.5V, I D = A f V GSth) Gate Threshold Voltage.4.3 V V DS = V GS, I D = 5µA V GSth) T J Gate Threshold Voltage Coefficient -6. mv C I DSS Drain-to-Source Leakage Current. µa V DS = 4V, V GS = V 5 V DS = 4V, V GS = V, T J = 5 C I GSS Gate-to-Source Forward Leakage na V GS = V Gate-to-Source Reverse Leakage - V GS = -V gfs Forward Transconductance 66 S V DS = 5V, I D = A Q g Total Gate Charge 33 5 Q gs Pre-Vth Gate-to-Source Charge 8. V DS = 6V Q gs Post-Vth Gate-to-Source Charge. nc V GS = 4.5V Q gd Gate-to-Drain Charge 3 I D = A Q godr Gate Charge Overdrive 9.9 See Fig. 6 Q sw Switch Charge Q gs Q gd ) 5 Q oss Output Charge nc t don) Turn-On Delay Time 4 t r Rise Time 6.9 t doff) Turn-Off Delay Time 3 ns t f Fall Time 5 C iss Input Capacitance 4 C oss Output Capacitance 95 pf C rss Reverse Transfer Capacitance 4 Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 53 mj I AR Avalanche Currentc A E AR Repetitive Avalanche Energy c 4 mj Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 4f Conditions V GS = V, I D = 5µA Reference to 5 C, I D = ma V GS = V, I D = 5A f V DS = 6V, V GS = V V DD = 5V, V GS = 4.5V f I D = A Clamped Inductive Load V GS = V V DS = 5V ƒ =.MHz Conditions MOSFET symbol D Body Diode) A showing the I SM Pulsed Source Current 56 integral reverse G Body Diode)ch p-n junction diode. S V SD Diode Forward Voltage. V T J = 5 C, I S = A, V GS = V f t rr Reverse Recovery Time 39 58 ns T J = 5 C, I F = A, V DD = 5V Q rr Reverse Recovery Charge 3 55 nc didt = Aµs f t on Forward Turn-On Time Intrinsic turn-on time is negligible turn-on is dominated by LSLD) www.irf.com
I D, Drain-to-Source Current Α) R DSon), Drain-to-Source On Resistance Normalized) I D, Drain-to-Source Current A) I D, Drain-to-Source Current A) IRLRU833 VGS TOP V 5.V 4.5V 3.5V 3.V.V.5V BOTTOM.5V VGS TOP V 5.V 4.5V 3.5V 3.V.V.5V BOTTOM.5V...5V µs PULSE WIDTH Tj = 5 C. V DS, Drain-to-Source Voltage V).5V µs PULSE WIDTH Tj = 5 C. V DS, Drain-to-Source Voltage V) Fig. Typical Output Characteristics Fig. Typical Output Characteristics.. T J = 5 C. I D = 3A V GS = V.5.. T J = 5 C. V DS = 5V µs PULSE WIDTH.. 3. 4. 5. 6. V GS, Gate-to-Source Voltage V).5-6 -4-4 6 8 4 6 8 T J, Junction Temperature C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3
I SD, Reverse Drain Current A) I D, Drain-to-Source Current A) C, CapacitancepF) V GS, Gate-to-Source Voltage V) IRLRU833 V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 6. 5. I D = A V DS = 4V V DS = 5V 4. C iss 3. C oss C rss... 3 4 5 V DS, Drain-to-Source Voltage V) Q G Total Gate Charge nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage. OPERATION IN THIS AREA LIMITED BY R DS on). T J = 5 C. µsec T. J = 5 C V GS = V...5..5..5 V SD, Source-to-Drain Voltage V) Tc = 5 C Tj = 5 C Single Pulse msec msec V DS, Drain-to-Source Voltage V) Fig. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
V GSth) Gate threshold Voltage V) IRLRU833 5.5 LIMITED BY PACKAGE 5. I D, Drain Current A) 5 5 5.5..5 I D = 5µA 5 5 5 5 5 5 T C, Case Temperature C). -5-5 -5 5 5 5 5 5 5 T J, Temperature C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature Thermal Response Z thjc ). D =.5...5.. SINGLE PULSE THERMAL RESPONSE). Peak T J = P DM x Z thjc T C...... t, Rectangular Pulse Duration sec) Notes:. Duty factor D = t t P DM t t Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
E AS, Single Pulse Avalanche Energy mj) IRLRU833 R G V DS V V GS tp L D.U.T IAS.Ω 5V DRIVER - V DD A 5 5 5 I D TOP 8.A 4A BOTTOM A Fig a. Unclamped Inductive Test Circuit 5 tp V BR)DSS 5 5 5 5 5 5 Starting T J, Junction Temperature C) Fig c. Maximum Avalanche Energy Vs. Drain Current I AS Fig b. Unclamped Inductive Waveforms V DS R D V GS D.U.T. R G - V DD Current Regulator Same Type as D.U.T. V GS Pulse Width µs Duty Factor. % 5KΩ V.µF.3µF Fig 4a. Switching Time Test Circuit D.U.T. V - DS V DS 9% V GS 3mA I G I D Current Sampling Resistors % V GS t don) t r t doff) t f Fig 3. Gate Charge Test Circuit Fig 4b. Switching Time Waveforms 6 www.irf.com
IRLRU833 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current didt D.U.T. V DS Waveform Diode Recovery dvdt D = P.W. Period V GS =V V DD * R G dvdt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dvdt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgsth) Qgs Qgs Qgd Qgodr Fig 6. Gate Charge Waveform www.irf.com
IRLRU833 Power MOSFET Selection for Non-Isolated DCDC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q. Power losses in the high side switch Q, also called the Control FET, are impacted by the R dson) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = I rms R dson ) ) I Q gd V in f I Q gs V in f i g ) Q g V g f Q oss V in f This simplified loss equation includes the terms Q gs and Q oss which are new to Power MOSFET data sheets. Q gs is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs, can be seen from Fig 6. Q gs indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q is approximated by; * P loss = P conduction P drive P output ) P loss = I rms R dson) ) Q g V g f Q oss V in f Q rr V in f *dissipated primarily in Q. ) For the synchronous MOSFET Q, R dson) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdvdt turn on. The drain of Q is connected to the switching node of the converter and therefore sees transitions between ground and V in. As Q turns on and off there is a rate of change of drain voltage dvdt which is capacitively coupled to the gate of Q and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd Q gs must be minimized to reduce the potential for Cdvdt turn on. Figure A: Q oss Characteristic 8 www.irf.com
IRLRU833 TO-5AA D-Pak) Package Outline Dimensions are shown in millimeters inches) 5.46.5) 5..5) 6.3.65) 6.35.5) - A -..5).88.35).38.94).9.86).4.45).89.35).58.3).46.8) 4..4).64.5).5.6).5.45) X.4.45).6.3) 3 3X 6..45) 5.9.35) - B -.89.35).64.5).5.) M A M B.4.4) 9.4.3) 6.45.45) 5.68.4).5.) MIN..58.3).46.8) LEAD ASSIGNMENTS - GATE - DRAIN 3 - SOURCE 4 - DRAIN.8.9) 4.5.8) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 98. CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-5AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX..6.6). TO-5AA D-Pak) Part Marking Information 5 % 8 5 3, 5, < 5 ) % 6,5,6,6, : 3 ; ' & ' 8 ),5 5,,) & 5 ' & 5 < * : : ' % 6. :, < % 6,, < % 6 ' & www.irf.com 9
IRLRU833 I-Pak TO-5AA) Package Outline Dimensions are shown in millimeters inches) 5.46.5) 5..5).5.6).5.45) 6.3.65) 6.35.5) - A - 4 6..45) 5.9.35)..5).88.35).38.94).9.86).58.3).46.8) 6.45.45) 5.68.4) LEAD ASSIGNMENTS - GATE - DRAIN 3 - SOURCE 4 - DRAIN 3 - B -.8.9).9.5) 9.65.38) 8.89.35) NOTES: DIMENSIONING & TOLERANCING PER ANSI Y4.5M, 98. CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-5AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX..6.6). 3X.4.45).6.3).8.9) X 3X.89.35).64.5).5.) M A M B.4.45).89.35).58.3).46.8) I-Pak TO-5AA) Part Marking Information www.irf.com
IRLRU833 D-Pak TO-5AA) Tape & Reel Information Dimensions are shown in millimeters inches) TR TRR TRL 6.3.64 ) 5..69 ) 6.3.64 ) 5..69 )..46 ).9.469 ) FEED DIRECTION 8..38 ).9.3 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER.. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 5 C, L =.6mH, R G = 5Ω, I AS = A. ƒ Pulse width 4µs; duty cycle %. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 3A. When mounted on " square PCB FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 945, USA Tel: 3) 5-5 TAC Fax: 3) 5-93 Visit us at www.irf.com for sales contact information.34 www.irf.com
Note: For the most current drawings please refer to the IR website at: http:www.irf.compackage