2416 EERM erial 16-b I 2 Description he 2416 is a EERM erial 16 b I 2 device internally organized as 2048x8 bits. he device features a 16 byte page write buffer and supports 100 khz, 400 khz and 1 MHz I 2 protocols. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a age Write Buffer, and then writing all data to non volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. Features tandard and Fast I 2 rotocol ompatible upports 1 MHz lock Frequency 1.7 V to 5.5 V upply Voltage Range 16 Byte age Write Buffer Hardware Write rotection for Entire Memory chmitt riggers and Noise uppression Filters on I 2 Bus Inputs (L and D) Low ower M echnology 1,000,000 rogram/erase ycles 100 Year Data Retention Industrial emperature Range his Device is b Free, Halogen Free/BFR Free and are RoH ompliant V IN NFIGURIN V D in Name D L L 1 23 B UFFIX E 419E 23 2 3 5 4 (op View) IN FUNIN W V Function erial Data Input/utput lock Input L W V Write rotect ower upply 2416 D V N Ground No onnect W V Figure 1. Functional ymbol RDERING INFRMIN ee detailed ordering and shipping information in the package dimensions section on page 203 of this data sheet. emiconductor omponents Industries, LL, 2009 May, 2018 Rev. 2 1 ublication rder Number: 2416/D
2416 able 1. BLUE MXIMUM RING arameters Ratings Units torage emperature 65 to +150 Voltage on any in with Respect to Ground (Note 1) 0.5 to +6.5 V tresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. he D input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. able 2. REBILIY HRERII (Note 2) ymbol arameter Min Units N END (Note 3) Endurance 1,000,000 rogram/erase ycles DR Data Retention 100 Years 2. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 3. age Mode @ 25 able 3. D ERING HRERII (V = 1.7 V to 5.5 V, = 40 to 85, unless otherwise specified.) ymbol arameter est onditions Min Max Units I R Read urrent Read, f L = 400 khz 0.5 m I W Write urrent Write, f L = 400 khz 1 m I B tandby urrent ll I/ ins at GND or V 1 I L I/ in Leakage in at GND or V 1 V IL Input Low Voltage 0.5 V x 0.3 V V IH Input High Voltage V x 0.7 V + 0.5 V V L1 utput Low Voltage V 2.5 V, I L = 3.0 m 0.4 V V L2 utput Low Voltage V < 2.5 V, I L = 1.0 m 0.2 V able 4. IN IMEDNE HRERII (V = 1.7 V to 5.5 V, = 40 to 85, unless otherwise specified.) ymbol arameter onditions Max Units IN (Note 4) D I/ in apacitance V IN = 0 V 8 pf IN (Note 4) Input apacitance (ther ins) V IN = 0 V 6 pf I W (Note 5) W Input urrent V IN < 0.5 x V, V = 5.5 V 200 V IN < 0.5 x V, V = 3.3 V 150 V IN < 0.5 x V, V = 1.8 V 100 V IN > 0.5 x V 1 4. hese parameters are tested initially and after a design or process change that affects the parameter according to appropriate E Q100 and JEDE test methods. 5. When not driven, the W pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. o conserve power, as the input level exceeds the trip point of the M input buffer (~ 0.5 x V ), the strong pull down reverts to a weak current source. 2
2416 able 5. HRERII (Note 6) (V = 1.7 V to 5.5 V, = 40 to 85, unless otherwise specified.) tandard V = 1.7 V 5.5 V Fast V = 1.7 V 5.5 V 1 MHz V = 2.5 V 5.5 V ymbol arameter Min Max Min Max Min Max F L lock Frequency 100 400 1000 khz t HD: R ondition Hold ime 4 0.6 0.25 s t LW Low eriod of L lock 4.7 1.3 0.4 s t HIGH High eriod of L lock 4 0.6 0.4 s t U: R ondition etup ime 4.7 0.6 0.25 s t HD:D Data In Hold ime 0 0 0 ns t U:D Data In etup ime 250 100 100 ns t R (Note 7) D and L Rise ime 1000 300 300 ns t F (Note 7) D and L Fall ime 300 300 100 ns t U: ondition etup ime 4 0.6 0.25 s t BUF Bus Free ime Between and R Units 4.7 1.3 0.5 s t L Low to Data ut Valid 3.5 0.9 0.4 s t DH Data ut Hold ime 100 50 50 ns i (Note 7) Noise ulse Filtered at L and D Inputs 100 100 100 ns t U:W W etup ime 0 0 0 s t HD:W W Hold ime 2.5 2.5 1 s t WR Write ycle ime 5 5 5 ms t U (Notes 7, 8) ower up to Ready Mode 1 1 1 ms 6. est conditions according to est onditions table. 7. ested initially and after a design or process change that affects this parameter. 8. t U is the delay between the time V is stable and the device is ready to accept commands. able 6... E NDIIN Input Levels Input Rise and Fall imes Input Reference Levels utput Reference Levels utput Load 0.2 x V to 0.8 x V 50 ns 0.3 x V, 0.7 x V 0.5 x V urrent ource: I L = 3 m (V 2.5 V); I L = 1 m (V < 2.5 V); L = 100 pf 3
2416 ower n Reset (R) Each 2416 incorporates ower n Reset (R) circuitry which protects the internal logic against powering up in the wrong state. he device will power up into tandby mode after V exceeds the R trigger level and will power down into Reset mode when V drops below the R trigger level. his bi directional R behavior protects the device against brown out failure, following a temporary loss of power. in Description L: he erial lock input pin accepts the clock signal generated by the Master. D: he erial Data I/ pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and delivered on the negative edge of L. W: When the Write rotect input pin is forced HIGH by an external source, all write operations are inhibited. When the pin is not driven by an external source, it is pulled LW internally. Functional Description he 2416 supports the Inter Integrated ircuit (I 2 ) Bus protocol. he protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and lave devices which execute requests. he 2416 operates as a lave device. Both Master and lave can transmit or receive, but only the Master can assign those roles. I 2 Bus rotocol he 2 wire I 2 bus consists of two lines, L and D, connected to the V supply via pullup resistors. he Master provides the clock to the L line, and the Master and laves drive the D line. 0 is transmitted by pulling a line LW and a 1 by releasing it HIGH. Data transfer may be initiated only when the bus is not busy (see haracteristics). During data transfer, D must remain stable while L is HIGH. R/ ondition n D transition while L is HIGH creates a R or condition (Figure 2). R is generated by a HIGH to LW transition, while a is generated by a LW to HIGH transition. he R acts like a wake up call. bsent a R, no lave will respond to the Master. he completes all commands. Device ddressing he Master addresses a lave by creating a R condition and then broadcasting an 8 bit lave address (Figure 3). he four most significant bits of the lave address are 1010 (h). he next three bits are internal address bits, a 10, a 9, a 8. he last bit, R/W, instructs the lave to either provide (1) or accept (0) data, i.e. it specifies a Read (1) or a Write (0) operation. cknowledge During the 9 th clock cycle following every byte sent onto the bus, the transmitter releases the D line, allowing the receiver to respond. he receiver then either acknowledges () by pulling D LW, or does not acknowledge (No) by letting D stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. L D R NDIIN NDIIN Figure 2. tart/top iming 1 0 1 0 a 10 a 9 a 8 R/W Figure 3. lave ddress Bits 4
2416 L FRM MER BU RELEE DELY (RNMIER) 1 8 9 BU RELEE DELY (REEIVER) D UU FRM RNMIER D UU FRM REEIVER R DELY ( t ) Figure 4. cknowledge iming EU ( t U:D ) t F t HIGH t R t LW t LW L t U: t HD: t HD:D t U:D t U: D IN t t DH t BUF D U Figure 5. Bus iming WRIE ERIN Byte Write o write data to memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 0. he Master then sends an address byte and a data byte and concludes the session by creating a condition on the bus. he lave responds with after every byte sent by the Master (Figure 6). he starts the internal Write cycle, and while this operation is in progress (t WR ), the D output is tri stated and the lave does not acknowledge the Master (Figure 7). age Write he Byte Write operation can be expanded to age Write, by sending more than one data byte to the lave before issuing the condition (Figure 8). Up to 16 distinct data bytes can be loaded into the internal age Write Buffer starting at the address provided by the Master. he page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the, data loaded during the age Write session will be written to memory in a single internal Write cycle (t WR ). cknowledge olling he acknowledge () polling routine can be used to take advantage of the typical write cycle time. nce the stop condition is issued to indicate the end of the host s write operation, the 2416 initiates the internal write cycle. he polling can be initiated immediately. his involves issuing the start condition followed by the slave address for a write operation. If the 2416 is still busy with the write operation, No will be returned. If the 2416 device has completed the internal write operation, an will be returned and the host can then proceed with the next read or write operation. Hardware Write rotection With the W pin held HIGH, the entire memory is protected against Write operations. If the W pin is left floating or is grounded, it has no impact on the Write operation. he state of the W pin is strobed on the last falling edge of L immediately preceding the 1 st data byte (Figure 9). If the W pin is HIGH during the strobe interval, the lave will not acknowledge the data byte and the Write request will be rejected. Delivery tate he 2416 is shipped erased, i.e., all bytes are FFh. 5
2416 BU IVIY: MER LVE DDRE D R DDRE a 7 a 0 d 7 d 0 LVE Figure 6. Byte Write equence L D 8 th Bit Byte n t WR NDIIN R NDIIN DDRE Figure 7. Write ycle iming BU IVIY: MER R LVE DDRE DDRE D n D n+1 D n+x LVE n = 1 x 15 Figure 8. age Write equence DDRE D 1 8 9 1 8 L D a 7 a 0 d 7 d 0 t U:W W t HD:W Figure 9. W iming 6
Immediate Read o read data from memory, the Master creates a R condition on the bus and then broadcasts a lave address with the R/W bit set to 1. he lave responds with and starts shifting out data residing at the current address. fter receiving the data, the Master responds with No and terminates the session by creating a condition on the bus (Figure 10). he lave then returns to tandby mode. elective Read o read data residing at a specific address, the selected address must first be loaded into the internal address register. his is done by starting a Byte Write sequence, whereby the Master creates a R condition, then broadcasts a lave address with the R/W bit set to 0 and then sends an address byte to the lave. Rather than completing the Byte Write BU IVIY: MER 2416 RED ERIN R LVE DDRE sequence by sending data, the Master then creates a R condition and broadcasts a lave address with the R/W bit set to 1. he lave responds with after every byte sent by the Master and then sends out data residing at the selected address. fter receiving the data, the Master responds with No and then terminates the session by creating a condition on the bus (Figure 11). equential Read If, after receiving data sent by the lave, the Master responds with, then the lave will continue transmitting until the Master responds with No followed by (Figure 12). During equential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. N LVE D L 8 9 D 8 th Bit D U N Figure 10. Immediate Read equence and iming BU IVIY: MER R LVE DDRE DDRE R LVE DDRE N LVE D BU IVIY: MER LVE DDRE Figure 11. elective Read equence N LVE D n D n+1 D n+2 Figure 12. equential Read equence D n+x 7
RDERING INFRMIN Device rder Number pecific Device Marking ackage ype 2416 emperature Range (Note 24) Lead Finish hipping 2402DI G3 U 23 5 Industrial Nidu ape & Reel, 3,000 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel ackaging pecifications Brochure, BRD8011/D. 9. ll packages are RoH compliant (Lead free, Halogen free). 10. he standard lead finish is Nidu. 11. For additional package and temperature options, please contact your nearest N emiconductor ales office. 12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel ackaging pecifications Brochure, BRD8011/D. N emiconductor is licensed by the hilips orporation to carry the I 2 bus protocol. 8
MEHNIL E ULINE GE DIMENIN 23, 5 LED E 419E 01 IUE DE 19 DE 2008 e D YMBL 1 MIN NM MX 1.00 0.01 0.05 0.10 2 0.80 0.87 0.90 b 0.30 0.45 c 0.12 0.15 0.20 E1 E D E 2.90 B 2.80 B E1 1.60 B e 0.95 Y L 0.30 0.40 0.50 L1 0.60 REF VIEW L2 θ 0.25 B 0º 8º 2 b 1 L1 L c L2 IDE VIEW END VIEW Notes: (1) ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE M-193. DUMEN NUMBER: U: REFERENE: emiconductor omponents Industries, LL, 2002 ctober, 2002 Rev. 0 DERIIN: 98N34392E N EMINDUR NDRD 23, 5 LED http://onsemi.com 1 Electronic versions are uncontrolled except when accessed directly from the Document Repository. rinted versions are uncontrolled except when stamped NRLLED Y in red. ase utline Number: GE 1 F XXX 2
DUMEN NUMBER: 98N34392E GE 2 F 2 IUE REVIIN DE RELEED FR RDUIN FRM D #235 005 01 N 19 DE 2008 EMINDUR. REQ. BY B. BERGMN. N emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal pportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. emiconductor omponents Industries, LL, 2008 December, 2008 Rev. 01 ase utline Number: 419E
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