SKA technology: RF systems & signal processing Mike Jones University of Oxford
SKA RF processing Dish receivers Cryogenics RF electronics Fast sampling Antenna processing AA receivers RF gain chain Sampling/antenna processing Beamforming
SKA dishes Baseline design: 15-m offset-gregorian dual reflectors Usable freq range 350 MHz 20 GHz Common (almost?) design for SKA-mid and SKA-survey (SKA-mid) Cooled singlepixel receivers up to 5 bands (single-piece composite reflectors)
SKA-mid receivers Ideal freq coverage 350 MHz - >14GHz contiguous. In practice good illumination difficult over ultra-wide bands, hence 3:1 maximum freq ratio per feed 1.8:1 maximum for critical bands 5 bands to cover range: Band 1: 350 1050 MHz (3:1) Band 2: 950 1760 MHz (1.8:1) Band 3: 1650 3050 MHz (1.8:1) Band 4: 2800 5180 MHz (1.8:1) Band 5: 4600 13800 MHz (3:1) Feed/OMT designs are crucial!
SKA-mid: cryogenics Essential to cool LNA/OMT/(feed) for noise performance Cooling technologies: Stirling cooler: low power (<100W), high temp (~80K), no cryopumping, serviceability? Gifford-McMahon: high power (>1kW), low temp (~10K), cryopumping, service interval? GM currently favoured
SKA-mid: receiver systems Design decisions: Feed/OMT types (dish optics design ) Manufacturing routes Multi-bands/receiver package? Cryogenic/vacuum design for manufacturing, reliability, servicing LNAs (MMIC/discrete?) Post-LNA receiver Design for production: 200/2000 off
SKA-mid: RF electronics LNAs RF gain, filters etc High-speed sampling (~5 GS/s, 4-8b) No downconversion (some bands) IF bands of 1, 2.5 GHz Sampled data rate off antenna 40-90 Gb/s Interface to signal transport/timing workpackage
Aperture Array receiver systems AA-low in Phase 1 (50 300 MHz) ~250,000 receiver elements Prototyping and development for higher frequency denser aperture arrays leading to Phase 2 AA-mid up to 1.4 GHz Difficulty per unit area scales as about ν 3
AA-low receiver 50 300 (?) MHz Post-LNA ~100 db gain, filtering, equalisation ~1 GHs/s sampling, ~8 bits Station beamforming requires ν/ν << λ/d ~ 1/1000 Power consumption cost is crucial: NRE + (unit cost x production volume) + α(running cost x lifetime) Production volume = 250,000 (Phase 1) > 1,000,000 (Phase 2)
AA-low antenna processor Analogue in (local to antenna or RFoF) ADC ADC Channelize Channelize e Data format and physical interface Digital out (antenna to bunker or local rack) Clock Can be developed as block (almost) independently of architecture Processing load only ~500 GMAC/s smallish chip compared to beamformer AA-low: 300 MHz RF (800 GS/s), ~8 bits, 2 channels. In-module ~1000 ch channeliser. Fibre out ~6 Gb/s. 250,000 off Timing data in
AA-low beamforming Baseline design: ~1000 stations, ~300 antennas each, ~1 beam/station/frequency AA consortium looking at these numbers Expectation is more beamforming Looking at architectures, implementations FPGAs for prototyping Routes from FPGAs to production quantities
Beamformer node In partial beamformer, only one level of coefficient multiplication Everything else is just adders! Implement b = M.v in blocks each block is a tile Ideal implementation (simplest connections) is node with N in = no elements in tile, N out = no of beams (average over bandwidth) Multiplier node M.v Coefficient matrix in + Adder node
Multiplier node properties Roughly equal worry is processing and I/O Amount of each is large and depends strongly on station properties no of elements and no of beams. Internal switching needs to assemble data vectors flexibly from input antenna streams this is only flexibility you need! Assuming each antenna data stream = 1 GS/s 4+4 bits = 8 Gb/s encoded on a 13 Gb/s serial interface If nbeams = 300, Nant(tile) = 100 Node needs 400 x 13 Gb/s interfaces and 300 x 100 x 1G = 30 TMAC/s If nbeams = 35 (possible with dual-band array) Node needs 135 x 6 Gb/s interfaces and 35 x 100 x 0.5G = 1.7 TMACS
Adder node All coefficients applied in multiplier node Adders just add Ideally structured so input BW proportional to N tiles, output BW proportional to N beams Eg in 300-beams, 100-tiles, 1GS/s: Needs 400 13 Gb/s interfaces, 77 TADD/s (assuming binary adder tree not the most efficient) 35-beams, 100-tiles, 0.5 GS/s: Needs 135 6 Gb/s interfaces, 4.5 TADD/s
Current implementations Roach II Uniboard Virtex 7 300-beam multiplier 35-beam multiplier 300- beam adder 35-beam adder I/O lines 8 x 13 Gb/s 12 x 13 Gb/s 96 x 13 Gb/s 400 x 13 Gb/s 135 x 6 Gb/s 400 x 13 Gb/s 135 x 6 Gb/s TMAC/s 1 4 1.7 30 1.7 77 4.5
Physical arrangement largely dictated by signal transport costs/practicalities (RF/copper, RF/fibre, digital/fibre)
Summary: technology opportunities (selected) RF feeds, LNAs Cryogenics, cryostat/receiver integrated design High-speed (>>GS/s) sampling, streaming processing High-volume, low-cost, low power ~1 GS/s sampling & streaming processing Low cost/power short-range signal transport (analogue/digital?)