Texas Instruments ISO7220A Process Review 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
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Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 ISO7220_RI Die Features 3 ISO7220_RI Die Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metals 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Bipolar Transistors 4 Isolation Capacitors 4.1 Isolation Capacitors Critical Dimensions 4.2 Isolation Capacitors Plan-View Analysis 4.3 Isolation Capacitors Cross-Sectional Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 ISO7220A Top Package View 2.1.2 ISO7220A Bottom Package View 2.1.3 ISO7220A Package X-Ray 2.1.4 ISO7220A Side 1 Package X-Ray 2.1.5 ISO7220A Side 2 Package X-Ray 2.1.6 ISO7220A Delayered Package Photograph 2.1.7 ISO7220_RI Die Photograph 2.1.8 ISO7220_RI Die Markings 2.1.9 ISO7220A_LE Die Photograph 2.1.10 ISO7220A_LE Die Markings A 2.1.11 ISO7220A_LE Die Markings B 2.1.12 Analysis Sites 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Double Bond Pad 2.2.6 Single Bond Pad 2.2.7 Bipolar Transistors, Poly Resistors, and Poly/Poly Capacitors 2.2.8 Isolation Capacitors 3 ISO7220_RI Die Process Analysis 3.1.1 Die Thickness 3.1.2 Die Edge 3.1.3 Die Edge Seal 3.1.4 General Structure 3.2.1 Bond Pad 3.2.2 Right Bond Pad Edge 3.3.1 Passivation 3.3.2 IMD 2 3.3.3 PMD and IMD 1 3.3.4 Poly Over LOCOS 3.4.1 Metal 3 Cross Section 3.4.2 Minimum Metal 3 Pitch 3.4.3 Minimum Metal 2 Pitch 3.4.4 Minimum Pitch Metal 1 3.5.1 Minimum Pitch Via 2 3.5.2 Via 1 and Contact to Diffusion 3.5.3 Contact to Poly
Overview 1-2 3.6.1 NMOS Transistor 3.6.2 Minimum Contacted Gate Pitch MOS Transistors 3.6.3 Poly/Poly Capacitor 3.6.4 Poly Resistor 3.7.1 NPN Bipolar Transistor Plan View 3.7.2 NPN Bipolar Transistor SEM 3.7.3 NPN Bipolar Transistor SCM 4 Isolation Capacitors 4.2.1 Isolation Capacitors with Overhang 4.2.2 Isolation Capacitors Top and Bottom Plate Areas 4.3.1 Isolation Capacitors Optical Overview 4.3.2 Large and Small Isolation Capacitor Pair Optical 4.3.3 Small Isolation Capacitor Optical 4.3.4 Large Isolation Capacitor SEM Overview 4.3.5 Isolation Capacitor Edge 4.3.6 Isolation Capacitor Edge Detail 4.3.7 Isolation Capacitor Top Plate Edge Detail 4.3.8 Isolation Capacitor Bottom Plate SRP 4.3.9 Bevel Sample SRP
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.1.1 Package, Die, and Bond Pad Sizes 3 ISO7220_RI Die Process Analysis 3.3.1 Dielectric Thicknesses 3.4.1 Metal Thicknesses 3.4.2 Metal Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 4 Isolation Capacitors 4.1.1 Isolation Capacitor Horizontal Dimensions 4.1.2 Isolation Capacitor Vertical Dimensions 5 Critical Dimensions 5.1.1 Package, Die, and Bond Pads 5.1.2 Minimum Pitch Metals 5.1.3 Minimum Pitch Contacts and Vias 5.1.4 Transistor Horizontal Dimensions 5.1.5 Isolation Capacitor Horizontal Dimensions 5.2.1 Dielectrics Vertical Dimensions 5.2.2 Metals Vertical Dimensions 5.2.3 Transistor Vertical Dimensions 5.2.4 Die and Well Vertical Dimensions 5.2.5 Isolation Capacitor Vertical Dimensions
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