Isolation Syste with Wireless Power Transfer for Multiple Gate Driver Supplies of a Mediu Voltage Inverter Keisuke Kusaka, Koji Orikawa and Jun-ichi Itoh Dept. of Energy and Environental Nagaoka University of Technology Nagaoka, Niigata, Japan kusaka@stn.nagaokaut.ac.jp Kazunori Morita and Kuniaki Hirao Research & Developent Group Meidensha Corporation Nuazu, Japan Abstract In this paper, a ultiple wireless power transfer syste for ultiple gate driver supplies of a ediu voltage inverter is developed. The proposed isolation syste achieves a galvanic isolation with an air-gap of 5 using a wireless power transfer with agnetic resonance coupling. It easily respects the standard of galvanic isolation, which is established by International electrotechnical coission (IEC). Moreover, the power is supplied fro one transitting board to six gate drivers without a solid agnetic core. In this paper, the isolation syste is developed and tested. It is clarified that the isolation syste transits power of not less than 3 W to each gate drivers beyond an air-gap. However, su of the output power of the each receiving board are liited up to approxiately 3.5 W because of a voltage drop in the equivalent series resistances of the transission coils. Keywords Galvanic isolation, Mediu voltage inverter, Wireless power transfer, Magnetic Resonance Coupling I. INTRODUCTION In recent years, syste voltage of a three-phase ediu voltage inverter for a otor drive syste is rising to 3.3 kv and 6.6 kv. In the ediu voltage inverter, galvanic isolations are required at gate driver supplies. The safety standards, which are established by IEC [1], have to be satisfied for safety. The safety standards require a iniu clearance of 14 and a creepage distance of 81 when a syste voltage of the inverter is 6.6 kv, a coparative tracking index (CTI) is 1 CTI < 4 and a pollution degree is two [1]. In general, isolation transforers with solid agnetic cores are used for a galvanic isolation. However, it causes an increase in a cost because it is typically custo-built. Moreover, the isolation transforer is huge in order to obtain a high isolation voltage. For exaple, a typical diension of the isolation transforer, which have an isolation voltage of 2 kv rs for 1 s, are 2 2 2 at a weight of approxiately 5.5 kg [2]. These transforers are placed at each gate driver supplies. In order to achieve a cost reduction and a downsizing of the isolation syste, a single-chip DC-isolated gate drive IC has been deonstrated [3-5]. It supplies power using a icrowave fro a botto layer of a sapphire substrate to a top layer. In this ethod, galvanic isolation is achieved by the sapphire substrate. It can downsize an isolation syste vastly. However, it does not satisfy the safety standards because both of an isolation distance and a creepage distance are not enough. Meanwhile, J. W. Kolar et al. proposed the isolation syste with using a printed circuit board (PCB) [6]. It achieves a galvanic isolation with a coreless transforer. In this syste, one transitting side transits power to a receiving side oneby-one (1 1). Thus, the systes are also required at each gate driver supply. Therefore the reduction of the volue is liited. In this paper, a galvanic isolation syste with a ultiple wireless power transfer syste with agnetic resonance coupling for a ediu voltage inverter is developed. The isolation syste transits power fro one transitting board to six receiving boards (1 6) beyond an air-gap of 5. Because all of the isolation syste is constructed by the PCBs. The isolation syste contributes a cost reduction and a downsizing of the isolation syste. Besides, the insulation with an air-gap of 5 easily respects IEC standard of a clearance and a creepage distance, when the syste voltage of the inverter is 6.6 kv. Moreover, the air-gap of 5 reduces a coon-ode current, which is induced by high dv/dt of the ediu voltage inverter, to a sall-signal circuit. II. PROPOSED ISOLATION SYSTEM A. Syste Configuration Fig. 1 shows the syste configuration of the developed galvanic isolation syste for a ediu voltage inverter. The isolation syste consists of the transitting board and six receiving boards. The power consuption in the gate drive units (GDUs) is supplied through the isolation syste fro the low-voltage power supply of 48 V in a ediu voltage inverter.
B. Rated Power of Gate Driver Supplies The isolation syste transits the power consuption of the gate drivers. In this subsection, required power of the each gate driver is calculated. Fig. 4 shows the five-level diode-claped ultilevel inverter as a ediu voltage inverter, which has a rated output voltage of 6.6 kv and a rated output power of 1 MVA [13]. Each switching device is a string of three 1.7-kV IGBTs connected in series. The power consuption of a gate resistance PG of an IGBT is calculated by (1) where fc is a switching frequency, Qg is total gate charge and VGE are gateeitter voltage of the IGBT. ( PG = f c + Qg + Qg )( + V GE + VGE ) (1) Fro eq. (1), the power consuption is calculated as about 5 15 15 15 Fig. 1. Syste configuration of the developed isolation syste. Power is transitted fro the transitting board to the six receiving boards by a wireless power transfer with agnetic resonance coupling. 6 Incidentally, agnetic resonance coupling achieves a wireless power transfer with a resonance with a high-quality factor Q of the transission coils in a iddle-range transission distance [7-12]. In this syste, 2.18 MHz is used as the transission frequency because a high-frequency transission is required in order to downsize the transission coils. Then the isolation syste does not require a transforer with a agnetic core. In the conventional syste, the transforer with a agnetic core prevents an isolation syste fro a cost reduction and a downsizing. In contrast, the isolation syste is constructed only by the PCBs in this syste. The PCBs can be anufactured easily in coparison with the transforer. Fig. 2 shows the positional relationship of the transitting board and the receiving boards. The axiu size of the syste is constrained up to 3 15 15 for a reason of the space liitations of the ediu voltage inverter. The receiving boards are placed at top and botto of the transitting board. Each distance between the receiving boards and the transitting board is kept at not less than 5 for the galvanic isolation. It contributes the high isolation voltage and a low coon-ode current through leakage capacitances. It is enough to fulfill the safety standards of IEC [1] when the operating voltage of the ediu voltage inverter is 6.6 kv. The transitting boards consist of a high-frequency inverter, a series resonance capacitor and a transitting coil for a wireless power transfer syste. The inverter is operated by a square-wave operation with an output frequency of 2.18 MHz because high-frequency operation is necessary in order to downsize the transission coils on the PCB. On the other hand, the receiving boards consist of a receiving coil, series resonance capacitor and a diode bridge rectifier. Fig. 3 shows the photograph of the prototype of the isolation syste. Each board is placed according to the Fig. 2. Table I indicates the specifications of transitting coil and receiving coils. Fig. 2. Placeents of each boards of the proposed isolation syste. The receiving boards are placed up and down to the transitting board. Each board are placed keeping an air-gap of 5. Fig. 3. Photograph of proposed isolation syste. 6 W where a switching frequency of the ediu voltage inverter is 1 khz, total gate charges ±Qg are ±1 nc and gate-eitter voltage is ±15 V. Note that the values, which is used in this calculation, are typical value of an IGBT (VCE = 17V, IC = 15 A). Considering a power loss in a gate driver circuit, power of at least 12 W is required per one receiving board as the output power of the isolation syste.
III. FREQUENCY CHARACTERISTICS WITH ELECTROMAGNETIC ANALYSIS In this section, the part of the wireless power transfer in the isolation syste is analyzed with the electroagnetic analysis with Agilent advanced design syste (ADS). In ADS, a 3-D odel is analyzed by the oentu ethod. Table I shows the specifications of the coils for the analysis. The isolation syste transits power with the wireless power transfer with the series resonance capacitors. The windings of the coils are ade up on the surfaces of the PCBs. In the syste, series resonance capacitor in the transitting side and series resonance capacitors in the receiving side, which is called as S/S resonance, are used. The resonance capacitors on the transitting board and the receiving boards are 13 pf and 7 pf, respectively. The wireless power transfer with S/S resonance type has an advantage copared to other ethod such as a series resonance and parallel resonance (S/P), parallel resonance and parallel resonances (P/P) fro the standpoint of the variation of a coupling coefficient and a load. The load characteristics do not affect the resonance frequency in S/S resonance. It is suitable characteristic for the isolation syste because the loads have different value in each GDU in the isolation syste. Also, the coupling coefficient does not affect the resonance frequency in the S/S resonance. The coupling coefficients vary aong the receiving boards. It eans that, the isolation syste with S/S resonance can be operated at a constant operating frequency without a coplex control. Fig. 5 presents the definition of S-paraeters. The S- paraeter is one of the ethods to express the characteristics of a ulti-terinal circuit. The relationship between a square root of input power and a square root of output power is expressed by the atrix shown as eq. (2) where a 1 is a square root of travelling power, b 1 is a square root of reflected power in the priary side, a 2 is a square root of travelling power and b 2 is a square root of reflected power in the secondary side. In this paper, the S-paraeters are used to analyze the characteristics of the isolation syste. a1 S = b1 S ( 1,1) S( 1,2) a2 ( ) ( ) 2,1 S 2,2 b2 Fig. 6 shows the definition of S-paraeters in the syste. In this consideration, a S-paraeter S(n,) is especially focused. The S-paraeter S(n,) is the ratio of a square root of power fro the transitting board to the receiving boards, where n is the nuber of the receiving boards (n = 1, 2,, 6). In the isolation syste, the power flow is liited to one-way; fro the transitting board to the receiving board. Thus, the transission fro the receiving boards (#n) to the transitting board (#) can be ignored. Fig. 7 shows the S-paraeters S(n,) of the syste. The S- paraeters S(2,) and S(5,) reach to -9 db at the resonance frequency. It eans that the each ratio of the output power of (2) Fig. 4. Assued 6.6 kv, 1 MVA five-level diode-claped ediu voltage invertere. Table I. Specification of coils. (a) Transitting coil. Ites Values Rearks Nuber of turn 12 turn Short type Width 25 Depth 4 Line width 1 Gap between windings.7 Thickness of PCB 1.6 FR-4 Fil thickness of copper 7 μ (b) Receiving coils. Ites Values Rearks Nuber of turns 4 turn Short type Outer diaeter 44 Inner diaeter 22 Gap between windings.4 Line width.2 Thickness of PCB 1.6 FR-4 S S ( i, i) S( i, j) ( j, i) S( j, j) Fig. 5. Definition of S-paraeters. the receiving boards (#2 and #5) to input power of the transitting board are 13.2%. In contrast, the S-paraeters S(1,), S(3,), S(4,) and S(6,) cannot reach to -1 db. Thus, the each ratio of the output power of the receiving boards (#1, #3, #4 and #6) to input power calculated as 7.4 %. The nonunifor transitted power is caused by the difference in the coupling coefficient aong the boards. The receiving boards, which are placed in center (#2 and #5) are coupled to the transitting board (#) strongly copared to other boards. Fig. 8 shows the effect between the abutting receiving
-2-4 -6-8 1 1.5 2 2.5 3 Fig. 6. S-paraeters in the isolation syste. All of the boards are nubered fro # to #6. All of the analyses with S-paraeters in this paper are held with a characteristic ipedance of 5 Ω. boards. The transission between the receiving boards is significantly sall than the transission between the transitting board (#) and the receiving boards (#1-6). For exaple, the transission fro the transitting board (#) to the receiving board (#1) S(1,) reaches to -11.4 db. On the other hand, the transission fro the receiving board (#2) to the receiving board (#1) S(1,2) is a -17.3 db. Thus, the coupling between the receiving boards can be ignored in the syste. Fig. 9 shows the siulated transission efficiency. The siulation is held without the converters such as an inverter and a rectifier. The transission efficiency expresses the ratio of su of the received power on the receiving boards to the transitted power fro the transitting board. Thus, the transission efficiency η Τ is calculated by (3). It should be noted that the output ipedance of the power supply and the load ipedance, which are used for an analysis, are 5 Ω. η = T S n= 1,2, 6 ( n,) 2 At a resonance frequency of 2.18 MHz, the total transission efficiency increases drastically because agnetic resonance coupling achieves the efficient wireless power transfer with a high quality factor Q. The axiu transission efficiency reaches to 53.6% at 2.18 MHz. In the isolation syste, low transission efficiency is accepted because the power loss in the proposed isolation syste is extreely low copared to the power loss of a ediu voltage inverter, typically. Thus, the power loss of the isolation syste can be ignored. IV. TIME-DOMAIN ANALYSIS A. Equivalent Circuit Fig. 1 presents the equivalent circuit of the wireless power transfer [14-15] where r -6 are the equivalent series resistances of the windings and C -6 are the series resonance capacitors. The equivalent circuit of the ultiple wireless power transfer (3) Fig. 7. Positional dependence of the receiving boards on the S- paraeters. The S-paraeters between the transitting board # and the receiving board #2, 5 are larger than the S-paraeter between the receiving board # and #1, 3, 4, 6. S(1,), S(1,2) [db] -2-4 -6-8 -1 1 1.5 2 2.5 3 Fig. 8. Effect between the abutting receiving board. The transission between the receiving boards such as S(1,2) is saller than the transission fro # to #1. 6 5 4 3 2 1 1 1.5 2 2.5 3 Fig. 9. Transission efficiency of the isolation syste. The efficiency is analyzed fro the 3-D odel with ADS. is obtained as transforers with ultiple windings where k is the coupling coefficient aong the each winding, which is expressed as (4). Note that, the subscript indicates the nuber of the transitting board. k1 k2 k6 k1 k12 k16 k = k 2 k21 k26 (4) k6 k61 k62 If the self-inductance of the each winding L is expressed as (5), the leakage inductance L le and agnetizing inductance L
are provided as (6) and (7), respectively. It should be noted that, k ij is equals to k ji (i, j =, 1,, 6). ( L L L L L L ) L = (5) 1 2 3 4 5 L6 L le = L L ( 1 1 1 1 1 1 1)k (6) L = Lk (7) The paraeters; the self-inductance, the series resonance capacitors and the coupling coefficients are introduced by the analysis results with ADS at the resonance frequency of 2.18 MHz. Table II shows the derived paraeters. In Fig. 1, the coupling coefficients aong the receiving boards are ignored because the effect of these coupling is significantly sall. It eans that the receiving boards are only agnetically coupled to the transitting board. Fig. 11 shows the coparison results of the frequency characteristics of the F-paraeters. The F-paraeters are copared between the equivalent circuit and the 3-D odel with ADS in frequency characteristics. ADS indicates the circuit characteristic as S-paraeters, typically. Thus, the analysis results are converted to the F-paraeters according to eq. (8). V A i = I C i 1 = 2S ji B V j D I j ( 1+ S )( ) {( )( ) } ii 1 S jj + S Sij + Sii + S jj S jisij Z ji 1 1 j 1 Z {( )( ) } {( )( + ) + } j 1 Sii 1 S jj S jisij 1 Sii 1 S jj S jisij Z i Z i The equivalent circuit odel shows the good agreeent with the 3-D odel. The error is caused by the unconsidered paraeters; parasitic capacitances between the layers of the PCB, parasitic capacitances between the windings and a dielectric loss of the PCB. These paraeters cannot be derived even by the siulation. Furtherore, the error occur owing to the non-linearly characteristics of an ipedance of the transission coils because the ipedance of the coils are not proportional to a frequency in the high-frequency region. However, the difference does not cause a fatal error on the tie-doain analysis. Thus, the operation odel is discussed using the equivalent circuit odel in the next subsection. B. Operation odes Fig. 12 shows the equivalent circuit with converters for the analysis of the operation odes of the syste. The series resonance capacitors are designed according to eq. (9) where ω sw is 2πf sw. The resonance capacitance C on the transitting board is selected in order to obtain a resonance with the selfinductance of the transitting coil. Siilarly, the resonance capacitances on the receiving boards are selected to resonate with the each self-inductance L of the receiving boards. (8) 1 = (9) L C 2 ω sw Fig. 1. Siplified equivalent circuit of the proposed isolation syste. 12 8 4-4 B 1 D 1 A 1 C 1 3-D odel (ADS) Equivalent circuit (PLECS) -8 1 2 3 4 Frequency f [MHz] Fig. 11. Coparison results of frequency characteristics between the 3-D odel with ADS and the equivalent circuit ode. Table II. Derived paraeter value fro the 3-D analysis. Ites Sybol Values Equivalent series resistances (ESRs) Self-inductances Coupling coefficients Board # r 12.9 Ω Board #1 r 1 11.7 Ω Board #2 r 2 11.6 Ω Board #3 r 3 11.7 Ω Board #4 r 4 11.7 Ω Board #5 r 5 11.6 Ω Board #6 r 6 11.7 Ω Board # L 41.8 μh Board #1 L 1 76.5 μh Board #2 L 2 75.9 μh Board #3 L 3 76.5 μh Board #4 L 4 76.5 μh Board #5 L 5 75.9 μh Board #6 L 6 76.5 μh k 1.16 k 2.26 k 3.25 k 4.16 k 5.26 k 6.25
Fig. 13 shows the vector diagras of the isolation syste. Owing to the resonance based on eq. (9), the inverter voltage and the current are in phase. The terinal voltage of the resonance capacitor and the inductance, becoe extreely high with opposite directions. Focusing on the receiving side, the resonance capacitor C 1 and the leakage inductance L le1 resonate. Fig. 14 illustrates the siplified operation wavefors of the isolation syste. 1) Mode I The inverter current i inv starts to flow through the MOSFETs and the coils because the MOSFETs S 1 and S 4 are turn-on. Owing to the resonance, the input current becoes a sinusoidal and it is in phase to the inverter output voltage v inv during a period. 2) Mode II The inverter current i inv coutates to the diodes D 2 and D 4 because the all of MOSFETs turn-off during the dead-tie T d. If the dead-tie is significantly short copared to the switching period, the MOSFETs achieve a zero current turnoff owing to the current resonance. After the half of the switching period, the inverter current crosses zero and coutate to the diodes D 1 and D 3. The inverter output voltage is decided by the polarity of the inverter output current. 3) Mode III The MOSFETs S 2 and S 4 turn-on. The inverter current coutates to the MOSFETs S 2 and S 4 fro the diodes. Also, the inverter current is sinusoidal owing to the resonances. 4) Mode IV The MOSFETs S 2 and S 4 have turned-off at the start of this ode. Owing to the current resonance, the MOSFETs turn-off around a zero current. It contributes a reduction of the switching loss. The inverter currents coutate to the diodes D 1 and D 4. The directions of the inverter current change to a positive fro a negative. V. EXPERIMENTAL RESULTS A. Fundaental Verifications Fig. 15 shows the operation wavefors with the prototype, which is shown in Fig. 3. Fig. 15 (a) is the wavefors with no-load condition. Fig. 15 (b) is the loaded wavefors with a resistance load of 17 Ω where the input power of the isolation syste is 31.3 W. In this experient, resistances are used instead of the gate drivers for siplicity. Fro the experiental wavefors, it is deonstrated that the wireless power transfer with an air-gap of 5 is achieved. An air-gap of 5 behaves as an isolation distance. Therefore, it is clear that the isolation syste satisfies the safety standards, which is established by IEC [1], when a syste voltage of the ediu voltage inverter is 6.6 kv. When the load is not connected, the rectifier input voltage v in1 is a sinusoidal because the diodes in the receiving boards do not turn-on. In contrast, the rectifier input voltage becoes Fig. 12. Equivalent circuit with converters. The ideal transforers are oitted for siplicity. Fig. 13. Vector diagra of the wireless power transfer. The series resonance capacitor C resonates with the su of leakage inductance L le and the agnetizing inductance L. The self-inductance L 2 and the series resonance capacitor C 1 resonate. Gate on S1,4 off on S2,3 v inv i inv i s1 i s2 i D1 i D2 v in1 off i in1 Mode I II III IV T 2 T Fig. 14. Siplified operation wavefors. The MOSFETs achieve a zero-current turn-off because of the current resonance. T d T d
a trapezoidal wave when the load is connected. This is caused by the sinusoidal-rectifier input current i in1. As an output voltage, a DC voltage V DC1 is obtained despite a load value. However, the output voltage decreases when the load is connected. It is caused by the voltage drop on the equivalent series resistances of the transission coils r -6. Incidentally, the others receiving boards siultaneously output the DC voltage. In this paper, the wavefors are oitted due to the page liitations. Fig. 16 shows the output power of each receiving board. The output power varies aong the position of the receiving boards. The difference between the output power is caused by the accuracy of the chassis and differences of the coupling coefficients. In the experiental setup, the output power of the receiving boards (#1, 2, 3) are saller than that of (#4, 5, 6), respectively because the difference in the transission distance occur between the upper boards and lower boards. Furtherore, the output power of the receiving boards #2 and #5 are larger than that of adjacent boards, respectively. Thus, the output power of #5 has axiu output power. The iniu output power reaches to 32 W. It is confired that the isolation syste supplies the power, which is required in the gate driver supplies. Fig. 17 shows the total output power P out_total characteristics. The total output power is calculated as (1). out n= 1,2,,6 ( n) P = P (1) out _ total (a) No-load. The output power increases as a load resistance decreases in the interval of the load resistance fro 125 Ω to 75 Ω. However, the output power stops to increase when the sall resistance such as 17 Ω is connected because the voltage drop on the equivalent series resistances of the transission coils increases owing to the increent of load current. B. Operation with Gate Drivers In this subsection, the prototype with the gate drivers is tested. The gate drivers, which are operated at a switching frequency of 1 khz, a gate-eitter voltage of ±15V, are connected as a load. Note that DC/DC converters as voltage regulators are connected at the front end of the gate drivers. The DC/DC converter output voltages of ±15 V. Moreover, the photocouplers (Toshiba, TLP25) are used in order to drive the IGBTs in spite of the deficient isolation distance because an isolation of the PWM signal is not a ain topic of this paper. Fig. 18 shows the operation wavefors where the capacitors of 33 nf is connected instead of the IGBTs. Even if the gate drivers are connected as a load, the operation syste achieves the wireless power transfer beyond an air-gap of 5. Fro the experiental results, it is confired that the proposed isolation syste can be used as an isolation syste for the ediu voltage inverter. (b) Loaded. Fig. 15. Operation wavefors. The load resistance of 17 Ω is connected as a load instead of a gate driver supplies. 12 1 8 6 4 2 Fig. 16. Operation wavefors. The output power varies aong the position of receiving boards. The difference of output power is caused by the difference in the accuracy of the chassis. VI. CONCLUSIONS In this paper, the isolation syste for gate drivers of a ediu voltage inverter with the syste voltage of 6.6 kv is reported. The isolation syste transits the power to the six gate drivers beyond the air-gap of 5. The isolation
distance satisfies the safety standards in IEC [1]. The isolation syste consists of the only seven PCBs. It contributes a cost and weight reduction because it does not need a agnetic core. The experiental results deonstrate that the isolation syste supplies the power of not less than 32 W to the each receiving boards. It is enough power to drive the IGBT in the ediu voltage inverter. REFERENCES [1] International Electrotechnical Coission (IEC): Adjustable speed electrical power drive systes Part 5-1: safety requireents Electrical, theral and energy, IEC 618-5-1 (27) [2] Christoph Marxgut, jurgen Biela, Johann W. Kolar, Reto Steiner, Peter K. Steier: DC-DC Converter for Gate Power Supplies with an Optial Air Transforer, Applied Power Electronics Conference and Exposition 21, pp. 1865-187 (21) [3] S. Nagai, N. Negoro, T. Fukuda, N. Otsuka, H. Sakai, T. Ueda, et al.: A DC-isolated gate drive IC with drive-by-icrowave technology for power switching devices, International Solid-State Circuits Conference 212, pp. 44-46 (212) [4] S. Nagai, T. Fukuda, N. Otsuka, D. Ueda, N. Negoro, H. Sakai, et al.: A one-chip isolated gate driver with an electroagnetic resonant coupler using a SPDT switch, 24th IEEE International Syposiu on Power Seiconductor Devices and ICs 212, pp. 73-76 (212) [5] S. Nagai, N. Negoro, T. Fukuda, H. Sakai, T. Ueda, T. Tanaka, et al.: Drive-by-Microwave technologies for isolated direct gate drivers, IEEE Microwave Workshop Series on Innovative Wireless Power Transission: Technologies, Systes, and Applications 212, Vol., No., pp. 267-27 (212) [6] R. Steiner, P. K. Steier, F. Kriser, J. W. Kolar: Contactless Energy transission for an Isolated 1W Gate Driver Supply of a Mediu Voltage Converter, 35th Annual Conference of the IEEE Industrial Electronics Society, pp. 32-37 (29) [7] S. Lee, R. D. Lorenz: Developent and Validation of Model for 95%- Efficiency 2-W Wireless Power Transfer Over a 3-c Air-gap, IEEE Trans. On Industry Applications, Vol. 47, No. 6, pp. 2495-254 (211) [8] T. Iura, Y. Hori: Maxiizing Air Gap and Efficiency of Magnetic Resonant Coupling for Wireless Power Transfer Using Equivalent Circuit and Neuann Forula, IEEE Trans. On Industrial Electronics, Vol. 58, No. 1, pp. 4746-4752 (211) [9] E. Waffenschidt, T. Staring: Liitation of inductive power transfer for consuer applications, European Conference on Power Electronics and Applications, pp. 1-1 (29) [1] S. Cheon, Y. Ki, S. Kang, M. L. Lee, J. Lee, T. Zyung: Circuit- Model-Based Analysis of a Wireless Energy-Transfer Syste via Coupled Magnetic Resonances, IEEE Trans. On Industrial Electronics, Vol. 58, No. 7, pp. 296-2914 (211) [11] A. P. Saple, D. A. Meyer, J. R. Sith: Analysis, Experiental results, and Range Adaptation of Magnetically Coupled Resonators for Wireless Power Transfer, IEEE Trans. On Industrial Electronics, Vol. 58, No. 2, pp. 544-554 (211) [12] S. Lee, R. D. Lorenz: A Design Methodology for Multi-kW, Large Airgap, MHz Frequency, Wireless Power Transfer Systes, IEEE ECCE 211, pp. 353-351 (211) [13] N. Hatti, Y. Kondo, H. Akagi: Five-Level Diode-Claped PWM Converters Connected Back-to-Back for Motor Drives, IEEE Trans. On Industry Applications, Vol. 44, No. 4, pp. 1268-1276 (28) [14] D. Ahn, S. Hong: A Study on Magnetic Field Repeater in Wireless Power Transfer, IEEE Trans. On Industrial Electronics, Vol. 6, No. 1, pp. 36-371 (213) [15] T. Iura: Equivalent Circuit for Repeater Antenna for Wireless Power Transfer via Magnetic Resonant Coupling Considering Signed Coupling, 6th IEEE Conf. On Industrial Electronics and Applications 211, pp. 151-156 (211) Total output power Pout (n) [W] n=1, 2,, 6 4 3 2 1 2 4 6 8 Fig. 17. Output power vs. load resistance. Owing to the voltage drop of the equivalent series resistance of the coils, the total output power is constrained at approxiately 3.5 W. (a) Gate-eitter voltage with proposed isolation syste. (b) Extended operation wavefors of (a). Fig. 18. Operation wavefors of the proposed isolation syste with the gate drivers.