An 8-Channel General-Purpose Analog Front- End for Biopotential Signal Measurement Group 4: Jinming Hu, Xue Yang, Zengweijie Chen, Hang Yang (auditing)
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
Input Signal Characteristics Brain Brain Heart Muscle 5μV ~ 5mV DC~2 khz
System Overview 8 Differential Pairs
Battery Characteristic Source: https://www.orbtronic.com/cr123a-16340-rechargeable-lithium-ion-700mah-orbtronic-battery
Block Diagram
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
Pre-Amplifier Goals 1. Input noise cancellation a. Chopper modulation 2. Provides 40 db gain with 2 khz bandwidth 3. Adjustable cutoff frequency for different biopotentials
Pre-Amplifier Topology Fully differential folded cascode amplifier PMOS diff pair first stage, common source second stage Cross coupled configuration High CMRR
Open-loop Characteristics DC Gain Phase Margin Bandwidth 58 db 70 degrees 0-8 khz Output Voltage 0-2.65 V
CMRR and PSRR 136 db from (0.5-2 khz) 90 db from (0.5-2 khz)
Chopper Implementation 1/f noise modulated to chopper frequency (15 khz) Subsequently eliminated by low pass filter
Adjustable High-pass Filter Nmos in series biased in subthreshold provides high resistance Tunable with gate voltage
Adjustable High-pass Filter
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
OTA Used in Gm-C Filter
2nd-Order Programmable Gm-C Filter gm4 gm1 gm2 gm3 Gm2 used to set cutoff frequency -biasing voltage is varied
Adjustable Low Pass Filter Cutoff frequency can vary from 255 Hz to 2.4 khz Capacitor at 3n -a bit large
Full Pre-amplification Stage 40 μv @ 1kHz Input
Pre-Amp and Gm-C Bandpass Response
Noise Analysis ~2.24μVrms in (0.5-2 khz)
Full Circuit
Performance Benchmarking
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
Channel Selector Logic Data Select Signals Output D 2 D 1 D 0 Y 0 0 0 S0 0 0 1 S1 0 1 0 S2 0 1 1 S3 1 0 0 S4 1 0 1 S5 1 1 0 S6 1 1 1 S7 Channel Selector
Channel Selector Logic Channel Selector
Channel Selector Logic Output Bit 0, 4, 7 Channel Selector
Buffer - Differential Difference Amplifier Buffer
DDA Open-loop Frequency Response Buffe r
DDA Close-loop Frequency Response Buffer
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier and BGR 6. Analog-Digital Converter
Bandgap Reference Generator Vbiasn = 0.75 V; Vbiasp = 2.3 V PGA
PGA Attempted Topology PGA
PGA Attempted Topology Can only reach a gain of 1. Moved to other typology. PGA
PGA Topology Fully differential sample and hold circuit from homework assignment. Fully differential amplifier comes from Baker 26.43. CH CH CF CF CH A = 1+CF/CH PGA
Amplification Signal, Gain = 2 PGA
Amplification Signal, Gain = 10 fclock = 500 K Vin f = 2K PGA
SW Cap Amp -- Clock Signals ph1, ph2, ph3 are non- overlapping. --A 5-transistor op-amp with a gain =1 transferring the fully differential amplifier s output signals into single ended signals to the ADC. PGA
1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter 4. 16-2 Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
ADC Architecture 8-bit SAR ADC Comparator SAR Logic Binary Weighted Capacitive DAC Charge Redistribution Architecture No s/h circuit Approaches Vcm at end of cycle
Comparator Design Output range ICMR Power Propagation Delay Rail to Rail 0-3.3 V < 396 uw 2.5 ns ADC
Comparator Layout
SAR Logic Schematic ADC
SAR Logic Layout ADC
DAC Schematic 1. Sampling phase 2. Hold phase 3. Charge redistribution phase ADC
One Throw Three Pole Switch Design ADC
ADC Conversion Cycle Voltage =.309 Digital Code = 00011000 ADC
Results Dynamic Range 0 V -2.0 V Power Consumption 478 μw ADC
Conclusion -- Collects EEG, ECoG, EMG, ECG signal from probes; --Processes EEG, ECoG, EMG, ECG signal for μc; -- Low power consumption (~890μW, ~270μA, 3.3V) -- Portable ready
Future Work -- Adding control abilities on channel switching; -- Review the order of system blocks; -- Possible power optimization; -- Command library; -- Integration of the voltage regulator (risky: heat diss.)
Block Diagram
Questions?