TM CDP8HC8W March 998 CMOS Serial Digital Pulse Width Modulator Features Programmable Frequency and Duty Cycle Output Serial Bus Input; Compatible with Motorola/Intersil SPI Bus, Simple Shift-Register Type Interface 8 Lead PDIP Package Schmitt Trigger Clock Input V to V Operation, -0 o C to 8 o C Temperature Range 8MHz Clock Input Frequency Pinout CDP8HC8W Description CS V T V SS (PDIP) TOP VIEW The CDP8HC8W modulates a clock input to supply a variable frequency and duty-cycle output signal. Three 8-bit registers (pulse width, frequency and control) are accessed 8 V DD Block Diagram INPUT MODULATOR LOGIC 8 - STAGE RIPPLE COUNTER 8 - STAGE RIPPLE COUNTER RESET PULSE - WIDTH REGISTER LOAD FREQUENCY REGISTER LOAD 8 - STAGE SHIFT REGISTER 8 - STAGE SHIFT REGISTER CONTROL REGISTER - STAGE SHIFT LOAD V T V T COMPARATOR 8 - STAGE - STATE COMPARATOR CS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -- Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00. All Rights Reserved File Number 99.
Absolute Maximum Ratings DC Supply Voltage Range, (V DD )................ -0.V to +V (Voltage Referenced to V SS Terminal) Input Voltage Range, All Inputs............. -0.V to V DD +0.V DC Input Current, Any One Input........................±0mA Operating Conditions Temperature Range (T A )...................... -0 o C to 8 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package............................. 99 Device Dissipation Per Output Transistor............... 00mW Maximum Storage Temperature Range (T STG )....- o C to 0 o C Maximum Lead Temperature (During Soldering).......... o C At Distance / ±/ in. (.9 ± 0.9mm) From Case for 0s Max T A = Full Package Temperature Range (All Package Types) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER SYMBOL MIN TYP MAX UNITS CDP8HC8W, V DD = V ±0%, V SS V, T A = -0 o C to 8 o C DC Operating Voltage Range - - V Input Voltage Range (Except V T Pin) V IH 0. V DD - V DD +0.V V V IL -0. - 0. V DD V V T Pin Output Voltage Threshold V IT 0. - 0. V DD V Device Current in Power Down Mode, Clock Disabled I PD - - µa Low Level Output Voltage (I OL =.ma) V OL - - 0. V High Level Output Voltage (I OH = -.ma) V OH V DD - 0.V - - V Input Leakage Current I IN - - ± µa Operating Device Current (f = MHz) I OPER - - ma Clock Input Capacitance (V IN V, f = MHz, T A = o C) C IN - - 0 pf Control Timing PARAMETER SYMBOL MIN MAX UNITS CDP8HC8W, V DD = V ±0%, V SS V, T A = -0 o C to 8 o C Clock Frequency F DC 8.0 MHz Cycle Time t CYC - - ns Clock to Out t O - ns Clock High Time t H 0 - ns Clock Low Time t L 0 - ns Rise Time (0% V DD to 0% V DD ) t R - 00 ns Fall Time (0% V DD to 0% V DD ) t F - 00 ns
SPI Interface Timing PARAMETER SYMBOL MIN MAX UNITS CDP8HC8W, V DD = V ±0%, V SS V, T A = -0 o C to 8 o C Serial Clock Frequency f DC. MHz Cycle Time t SCYC 80 - ns Enable Lead Time t ELD 0 - ns Enable Lag Time t ELG - 00 ns Serial Clock () High Time t SH 90 - ns Serial Clock () Low Time t SL 90 - ns Data Setup Time t DSU 00 - ns Data Hold Time t DHD 00 - ns Fall Time (0% V DD to 0% V DD, C L = 00pF) t F - 00 ns Rise Time (0% V DD to 0% V DD, C L = 00pF) t R - 00 ns t CYC t H t R t F t L t O t O FIGURE. TIMING CS (INPUT) t SCYC (INPUT) t ELD t F t ELG t SH t SL tr (INPUT) MSB LSB tdsu t DHD FIGURE. SERIAL PERIPHERAL INTERFACE TIMING
CHIP SELECT (CS) SERIAL () MSB DON T CONTROL WORD DON T DON T DON T DON T LSB DON T PWR CLOCK COUNT DIVIDE 0 MSB BIT BIT FREQUENCY WORD BIT BIT BIT CURVES CONTINUED IMMEDIATELY BELOW -OUT (CS) FREQUENCY WORD LSB MSB PULSE WIDTH () WORD LSB 0 0 BIT = BIT BIT 0 BIT BIT BIT BIT BIT BIT BIT BIT 0 = -OUT CURVES CONTINUED BELOW OUT INPUT CLOCK () OUTPUT () TOTAL OUTPUT PERIOD = X (INPUT CLOCK PERIOD) FIGURE. CDP8HC8W INTERFACE TIMING SPECIFICATIONS (CONTINUED)
Introduction The digital pulse width modular (D) divides down a clock signal supplied via the input as specified by the control, frequency, and pulse width data registers. The resultant output signal, with altered frequency and duty cycle, appears at the output of the device on the pin. Functional Pin Description V DD and V SS These pins are used to supply power and establish logic levels within the. V DD is a positive voltage with respect to V SS (ground). The pin is an input only pin where the clock signal to be altered by the circuitry is supplied. This is the source of the output. This input frequency can be internally divided by either one or two, depending on the state of the CD bit in the control register. CS The CS pin is the chip select input to the s SPI interface. A high-to-low ( to 0) transition selects the chip. A lowto-high (0 to ) transition deselects the chip and transfers data from the shift registers to the data registers. VT The VT pin is the input to the voltage threshold comparator on the. An analog voltage greater than 0.V (at V DD = V) on this pin will immediately cause the output to go to logic 0. This will be the status until the V T input is returned to a voltage below 0.V, the W is deselected, and then one or more of the data registers is written to. An analog voltage on this pin less than 0.V (at V DD = V) will allow the device to operate as specified by the values in the registers. Data input at this pin is clocked into the shift register (i.e., latched) on the rising edge of the serial clock (), most significant bits first. The pin is the serial clock input to the s SPI interface. A rising edge on this pin will shift data available at the () pin into the shift register. This pin provides the resultant output frequency and pulse width. After V DD power up, the output on this pin will remain a logic 0, until the chip is selected, bits of information clocked in, and the chip deselected. Functional Description Serial Port Data are entered into the three D registers serially through the pin, accompanied by a clock signal applied to the. The user can supply these serial data via shift register(s) or a microcontroller s serial port, such as the SPI port available on most CDP8HC0 microcontrollers. Microcontroller I/O lines can also be used to simulate a serial port. Data are written serially, most significant bit first, in 8, or -bit increments. Data are sampled and shifted into the s shift register on each rising edge of the. The serial clock should remain low when inactive. Therefore, when using a 8HC0 microcontroller s SPI port to provide data, program the microcontroller s SPI control register bits CPOL, CPHA to 0, 0. The CDP8HC8W latches data words after device deselection. Therefore, CS must go high (inactive) following each write to the W. Power-Up Initialization Upon V DD power up, the output of the chip will remain at a low level (logic zero) until:. The chip is selected (CS pin pulled low).. -bit of information are shifted in.. The chip is deselected (CS pin pulled high). The -bits of necessary information pertain to the loading of the 8-bit registers, in the following order:. Control register. Frequency register. Pulse width register See section entitled Pulse Width Modulator Data Registers for a description of each register. Once initialized, the specified output signal will appear until the device is reprogrammed or the voltage on the V T pin rises above the specified threshold. Reprogramming the device will update the output after the end of the present output clock period. Reprogramming Shortcuts After the device has been fully programmed upon power up, it is only necessary to input 8 bits of information to alter the output pulse width, or bits to alter the output frequency. Altering the Pulse Width: The pulse width may be changed by selecting the chip, inputting 8 bits, and deselecting the chip. By deselecting the chip, data from the first 8-bit shift register are latched into the pulse width register ( register). The frequency and control registers remain unchanged. The updated information will appear at the output only after the end of the previous total output period. Altering the Frequency: The frequency can be changed by selecting the chip, inputting bits (frequency information
followed by pulse width information), and deselected the chip. Deselection will transfer bits of data from the shift register into the frequency register and PW register. The updated frequency and PW information will appear at the output pin only after the end of the previous total output period. Altering the Control Word: Changing the clock divider and/or power control bit in the CDPHC8W control register requires full -bit programming, as described under Power Up Initialization. Pulse Width Modulator Data Registers Byte : Control Register 0 0 0 0 0 0 0 B-B Unused; don t care. B, PC Power Control Bit. If this bit is a 0, the chip will remain in the active state. If the bit is set to a, internal clocking and the voltage comparator (VT) circuit and voltage reference will be disabled. Thus the chip will enter a low current drain mode. The chip may only reenter the active mode by clearing this bit and clocking in a full bits of information. B0, CD Clock Divider Bit. If this bit is a 0, the chip will set internal clocking () at a divide-by-one rate with respect to the (). If this bit is set to, the internal clocking will be set to divide-by- state. Byte : Frequency Data Register B-B0 PC CD 0 Frequency Register This register contains the value that will determine the output frequency or total period by: F IN F OUT = ------------------------------------------ ( N + ) ( CD + ) F OUT = resultant output frequency F IN = the frequency of input n = value in frequency register CD = value of clock divider bit in control register. For a case of n (binary value in frequency register) equal to, CD (clock divider) (divide-by-), the output will be a frequency / that of the input clock (). Likewise, the output clock period will be equal to input periods. Byte : Pulse Width Data Register 0 B-B0 This register contains the value that will determine the pulse width or duty cycle (high duration) of the output waveform. PW = (N+) (CD+) PW = Pulse width out as measured in number of input periods. CD = Value of clock divider bit in control register. N = Value in PW register. For a case of n (binary value in PW register) equal to and CD (clock divider) (divide-by- ), the output will be input clock periods of a high level followed by the remaining clocks of the total period which will be a low level. Assuming the frequency register contains a value of, the resultant output would be high for periods, low for. Using the CDP8HC8W Programming the CDP8HC8W. Select chip. Write to control register. Write to frequency register. Write to pulse width register. Deselect chip NEXT - TO then alter the pulse width. Select chip. Write to pulse width register*. Deselect chip OR - To then alter the frequency (and possibly PW):. Select chip. Write to frequency register*. Write to pulse width register*. Deselect chip NOTE: All writes use 8-bit words Example when CD, Pulse Width Data Register When CD=0, frequency register =, pulse width register = ; output = high for input periods, low for ;. Select chip. Then write (most significant bit first) to the control, the frequency, and pulse width registers (control 0, frequency = 0, PW = )
. Deselect the chip New pulse width out begins and goes high when CS is raised after last pulse (assuming no previous time-out). then toggles on falling edges. Resulting output waveform: Control 0 = Divide-by-, frequency = ; PW = : ( + ) (0 + ) = s high time. Frequency INP = ------------------------------------- = ( 0 + ) ( 0 + ) INP ----------------------- CDP8HC8W Application Example The following example was written for a system which has the CDP8HC8W connected to the SPI bus of a CDP8HC0C8B microcontroller. The program sets the W to run a divide by 00 frequency with a duty cycle of 0% by writing to the Control Register, the Frequency Data Register, and the Pulse Width Data Register. The frequency and pulse width are then modified. Finally the pulse width is modified without changing the frequency. The program was assembled using the Intersil HASM.0 assembler. INTERSIL Corporation (c)990-99 8HC0 Assembler Version.0. Filename: W.LST Source Created:0/08/98, 0: am Assembled: 0/08/98, 0: am 0000 *********************************************************************** 0000 * File: W.S 0000 * Example W routines - sets W to a divide by 0000 * 00 output with 0% duty cycle 0000 * 0000 * Date: Thursday, January 8, 998 0000 *********************************************************************** 00008 00009 *********************************************************************** 0000 * Partial Map of CDP8HC0C8B Hardware Registers 000 *********************************************************************** 000 000 0000 Section Registers, $0000 000 0000 PortA ds ;Port A 000 000 PortB ds ;Port B 000 000 PortC ds ;Port C 000 000 PortD ds ;Port D 0008 000 DDRA ds ;Port A Data Direction Register 0009 000 DDRB ds ;Port B DDR 0000 000 DDRC ds ;Port C DDR 000 000 _Free ds ;three unused locations 000 000A SPCR ds ;SPI Control Register 000 $000 = SPE equ ;SPI Enable bit 000 $000 = MSTR equ ;SPI Master Mode bit 000 000B SPSR ds ;SPI Status Register 000 $000 = SPIF equ ;SPI Flag bit for ANDs, CMPs, etc. 000 000C SPDR ds ;SPI Data Register 0008 0009 *********************************************************************** 0000 * CDP8HC8W Constants 000 *********************************************************************** 000 000 $0000 W equ 0 ;W is connected to bit 0 of Port A 000 $000 = W_PC equ ;Power Control: = power down 000 $000 = W_CD equ ;Clock Divider: = divide by 000 000 0008 *********************************************************************** 0009 * Main Routines 0000 *********************************************************************** 000 000 000 Section Code, $000 000 000* [] 000 AD jsr Init_W ;turn on PA0 000 Set00_0 000 [] 00 00 bclr W,PortA ;select W (CE is active low) 000* [] 00 AD8 jsr Set_SPI_Mode ;Setup the 8HC0 SPI control 0008 ;to talk to the W 0009
0000 ******* Set Up Control, Frequency, and Pulse Width 000 000 SendCommands 000 [] 00 A0 lda #W_CD ;set divide by two clock on W 000* [] 008 AD9 jsr SPI_xmit 000 [] 00A A lda #99 ;set frequency to divide by 000 000* [] 00C AD jsr SPI_xmit 000 [] 00E AD lda #9 ;set pulse width to 0% duty cycle 0008* [] 00 AD jsr SPI_xmit 0009 0000 DeselectW_ 000 [] 0 000 bset W,PortA ;deselect the W which loads registers 000 ; with values transmitted 000 000 ; 000 ; Here the CDP8HC0C8B would generally 000 ; attend to other processing issues 000 ; 0008 0009 ******* Modify Frequency and Pulse Width 0000 000 [] 0 00 bclr W,PortA ;select W (CE is active low) 000* [] 0 AD jsr Set_SPI_Mode ;Setup the CDP8HC0 SPI Control... 000 ;to talk to the W 000 SendCommands 000 [] 08 A lda #9 ;set frequency to divide by 00 (the 000* [] 0A AD jsr SPI_xmit ;divide by is still in effect) 000 [] 0C A09 lda #9 ;set pulse width to 0% duty cycle 0008* [] 0E AD jsr SPI_xmit 0009 00080 DeselectW_ 0008 [] 00 000 bset W,PortA ;deselect the W which loads registers 0008 0008 ; 0008 ; Here the CDP8HC0C8B would again 0008 ; attend to other processing issues 0008 ; 0008 00088 ******* Modify Pulse Width 00089 00090 [] 0 00 bclr W,PortA ;select W (CE is active low) 0009* [] 0 AD08 jsr Set_SPI_Mode ;Setup the 8HC0 SPI control... 0009 ;to talk to the W 0009 SendCommands 0009 [] 0 A lda # ;set pulse width to 8% duty cycle 0009* [] 08 AD09 jsr SPI_xmit 0009 0009 DeselectW_ 00098 [] 0A 000 bset W,PortA ;deselect the W which loads registers 00099 ;with values transmitted 0000 Finish 000 [] 0C 0FE bra * ;loop forever 000 000 *********************************************************************** 000 * Common Subroutines 000 *********************************************************************** 000 000 0E Section Subroutines, * 0008 0009 Set_SPI_Mode 000 [] 0E A0 lda #(!SPE+!MSTR) ;Enable SPI as a Master with... 00 [] 00 B0A sta SPCR ;CPHA=CPOL=0, 00 [] 0 8 rts 00 SPI_Xmit 00 [] 0 B0C sta SPDR ;send A to SPI device 00 SPI_wait 00 [] 0 0F0BFD brclr SPIF,SPSR,SPI_wait ;wait until transmit complete 00 [] 08 8 rts 008 009 Init_W 000 [] 09 000 bset W,PortA ;disable the W (CE is active low) 00 [] 0B 00 bset W,DDRA ;by activating PA0 as a high 8
Dual-In-Line Plastic Packages (PDIP) CDP8HC8W INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E -B- A 0.00 (0.) M C A A L B S NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E8., E., E8., E8., E. will have a B dimension of 0.00-0.0 inch (0. -.mm). A e C E C L e A e B C E8. (JEDEC MS-00-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.0 -. A 0.0-0.9 - A 0. 0.9.9.9 - B 0.0 0.0 0. 0.8 - B 0.0 0.00.. 8, 0 C 0.008 0.0 0.0 0. - D 0. 0.00 9.0 0. D 0.00-0. - E 0.00 0.. 8. E 0.0 0.80.0. e 0.00 BSC. BSC - e A 0.00 BSC. BSC e B - 0.0-0.9 L 0. 0.0.9.8 N 8 8 9 Rev. 0 /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9