CMOS Cascode Transconductance Amplifier Basic topology. 5 V I SUP v s V G2 M 2 iout C L v OUT Device Data V Tn = 1 V V Tp = 1 V µ n C ox = 50 µa/v 2 µ p C ox = 25 µa/v 2 λ n = 0.05 V 1 λ p = 0.02 V 1 @ L = 2 µm V BIAS (a) (b) Current supply must have a very high source resistance r oc since otherwise it will limit the output resistance of the amplifier
Current Supply Topology p-channel cascode current supply is a obvious solution 5 V V G4 M 4 I SUP V G3 M 3 i OUT V G2 M 2 C L v OUT v s V BIAS need to design a totem pole voltage supply to generate V G2, V G3, and V G4
Totem Pole Voltage Reference Match device sizes of M 2B, M 3B, and M 4B to M 2, M 3, and M 4 5 V M 4B V G4 M 3B V G3 M 2B V G2 I REF
Complete Transconductance Amplifier V BIAS : user must supply a very precise DC voltage V BIAS 1.2 V so that the CS/CGcascode is biased so that it is in the high gain region 5 V M 3.5 V 4B M 4 = 200/2 M 2 = M 2B = 50/2 M 3 = M 3B = 64/2 M 3B 3.5 V M 3 M 4 = M 4B = 64/2 i OUT M 2B M 2 C L v OUT 0.6 V IREF = 100 µa v s V BIAS 1.2 V Overall two-port parameters: G m = g m1 Output resistance: R out = r o2 (1 g m2 r o1 ) r o3 (1 g m3 r o4 ) Output swing: V OUT(max) = V D4 - V SD3(sat) = V DD - V SG4B - V SG3B V SG3 - V SD3(sat) V OUT(max) = 5 V - 1.5 V - 1.5 V 1.5 V - 0.5 V = 3.0 V V OUT(min) = V D1 V DS2(sat) = V G2 - V GS2 V DS2(sat) = 2 V - 1.4 V 0.4 V = 1 V
Multistage Voltage Amplifier Example to understand a complicated circuit 5 V R 35 kω 100 µa M 7B M 6B Q 2B 3.5 V M 7 M 6 Q 2 3.0 V 1.5 V M 5 M 3 4.5 V 3.5 V 3.0 V 3.8 V 2.8 V 2.3 V Q 4 v OUT v s M 8 1.5 V M9 V BIAS 0 10 MOSFETs, 3 BJTs, 1 resistor... must identify building blocks Step-by-step approach to identifying the important transistors -- 1. replace all transistor current sources and voltage sources by their symbols -- look for diodes and current mirrors! (M 5, M 6 /M 6B, M 7 /M 7B, and 0 and Q 2B are part of current sources or a totem pole voltage reference.) 2. for the (few) remaining transistors, identify the type and use two-port smallsignal models to understand the circuit s operation. (For the above amplifier, the remaining transistors are, Q 2, M 3, and Q 4.)
Eliminating Current and Voltage Sources Replace current and voltage sources with symbols V DD = 5 V -I D5 -I D6 Q 4 M 3 V B2 Q 2 v OUT v s _ V BIAS _ I D10
Identifying Amplifier Stages n-channel MOSFET has its source grounded --> common source npn BJT Q 2 has its gate tied to a voltage source (from totem pole string of diode-connected transistors) --> common base p-channel MOSFET M 3 has its drain connected to ground --> common drain npn BJT Q 4 has its collector tied to the positive supply --> common collector Voltage amplifier is a cascade of two-port models: CS CB CD CC R in R out(cs/cb) R out 1. common source/common base with cascoded current-source supply: very high output resistance R out (CS/CB) --> can get extremely high output resistance, with a transconductance equal to that of the CS stage 2. common drain: no loading on previous stage since infinite input resistance 3. common collector: low output resistance
Cascode Stage Output Resistance Cascode input stage output resistance determines gain V DD = 5 V -I D6 R out,cb/cs V B2 Q 2 V BIAS _ 2 Output resistance: note that 2 = r o1 >> r π2 R out,cb = ( β o2 r o2 ) r oc6 = ( β o r o2 ) ( r o6 ( 1 g m6 r o7 ))
Overall Two-Port Parameters Since CC and CD stages have unity gain (approximately), we can quickly estimate the voltage gain by finding v in3 /v in where v in3 is the input to the CD stage Voltage gain: A v ( g m1 )R out,cb = g m1 (( β o r o2 ) ( r o6 ( 1 g m6 r o7 ))) Output resistance: source resistance of CC output stage is relatively small, since it preceded by a CD stage. 1,CC R out = R out,cc --------- ----------------- g m4 β o4 = 1 --------- g m 4 1 ------------------ g m 3 β o 4
DC Bias and Output Swing Assuming all n-channel devices have V GS = 1.5 V and p-channel devices have V SG = 1.5 V, we can find all the node voltages... we also assume that V BIAS has been adjusted such that the circuit is in the high-gain region 5 V R 35 kω 100 µa M 7B M 6B Q 2B 3.5 V M 7 M 6 Q 2 3.0 V 1.5 V M 5 M 3 4.5 V 3.5 V 3.0 V 3.8 V 2.8 V 2.3 V Q 4 v OUT v s M 8 1.5 V M9 V BIAS 0 Output swing: must consider more than output stage to find limits to V OUT
Frequency Response Before starting, review phasor analysis, Bode plots... Key concept: small-signal models for amplifiers are linear and therefore, cosines and sines are solutions of the linear differential equations which arise from R, C, and controlled source (e.g., G m ) networks. It is much more efficient to work with imaginary exponentials rather than cosine and sine functions; the measured function v(t) is considered (by convention) to be the real part of this imaginary exponential vt () = vcos( ωt φ) Re( ve ( jωt φ) ) = Re ve jφ e jωt ( ) where v is the amplitude and φ is the phase of the sinusoidal signal v(t). The phasor V is defined as the complex number V = ve jφ Therefore, the measured function is related to the phasor by vt () = Re( Ve jωt )
Circuit Analysis with Phasors The current through a capacitor is proportional to the derivative of the voltage: d it () = C vt () dt We assume that all signals in the circuit are represented by sinusoids. Substitution of the phasor expression for voltage leads to: vt () Ve jωt Ie jωt d jωt = C ( Ve ) = jωcve jωt dt which implies that the ratio of the phasor voltage to the phasor current through a capacitor (the impedance) is Zjω ( ) V = --- = I 1 ---------- j ω C Implication: the phasor current is linearly proportional to the phasor voltage, making it possible to solve circuits involving capacitors and inductors as rapidly as resistive networks... as long as all signals are sinusoidal.
Phasor Analysis of the Low-Pass Filter Voltage divider with impedances -- R V in C V out Replacing the capacitor by its impedance, 1 / (jωc), we can solve for the ratio of the phasors V out / V in V out ---------- V in = 1/jωC ------------------------- R 1/jωC multiplying by jωc/jωc leads to V out ---------- V in = 1 ----------------------- 1 j ω RC