A low noise amplifier with improved linearity and high gain

International Journal of Electronics and Computer Science Engineering 1188 Available Online at www.ijecse.org ISSN- 2277-1956 A low noise amplifier with improved linearity and high gain Ram Kumar, Jitendra Mishra Dept. of ECE NIT Sichar Silchar, Assam, India 1- ramkumar.purnea@gmail.com, 2- jeetu.er@gmail.com Abstract - In this paper presents a optimization of linearity of low noise amplifier by using post linearization techniques. in this technique we have used diode connected mosfet as IMD sinker also used interstage matching for gain enhancement and reducing the effect of nonlinearity in common gate stage of cascode amplifier, this has done by using UMC.18um CMOS Technology in cadence tool. We got gain 14dB, noise figure 2.1dB, IIP3 3.19dBm with power supply of 1.8v, and power consumption is 10.8mw. Keywords: Cascode amplifiers, post linearization, current source, interstage matching. 1. INTRODUCTION Low noise amplifiers (LNAs) are widely used in wireless communications. They can be found in almost all RF and microwave receivers in commercial applications. Linearity, power, noise, and gain are important design issues in the LNA design for modern wireless receivers. Since the LNA is the first block in the receiver chain, it must be sufficiently linear to suppress interference and maintain high sensitivity. To improve the linearity of the cascode LNA, several linearization methods have been proposed. To suppress the nonlinearity of the amplifier, the third-order derivative coefficient has to be close to zero. The optimum gate biasing technique was reported, and it showed that a FET can be linearized by biasing at a gate-to-source voltage (VGS) at which the third-order derivative of its dc transfer characteristic is zero. The major drawback of this technique is that the transistor has to be biased at the sweet spot, therefore, Limiting the transconductance of the input stage leading to reduced gain and increased NF. The multiple gated transistors (MGTR) technique[8-9] which falls under the category of feed forward, uses two transistors connected in parallel and biased in weak and strong inversion region, respectively. The auxiliary transistor generates a positive third-order derivative of the dc transfer characteristic (gm3) to cancel the negative gm3 generated by the main transistor. This results in increased linearity with wide DC operating range. However, the penalty of using this method is that the weak inversion transistor connected to the input degrades the NF of the LNA. Moreover, the bias circuit of each sub-amplifier circuit is independent, and constantly consumes DC power. To overcome these drawbacks, we present a novel post-linearization technique for the cascode CMOS LNA with the concept of IMD sinking. In the proposed method, the IMD3 can be partially canceled by the additional folded diode with a parallel RC circuit. 2. DESIGN OF CMOS LNA Conventionally, in designing the CMOS cascode LNA, the common-gate (CG) stage is assumed as an ideal current buffer which delivers the drain current of the CS stage to the output load. Accordingly, the linearity of the cascode amplifier has been considered to be mainly determined by the nonlinearity of the CS stage. Therefore, most of the previous works to improve the linearity of CMOS LNAs have focused on improving the linearity of the CS stage. However, as the operating frequency and the gain increase, the CG stage limits the linearity of the cascode amplifier. Though the nonlinearity of the CG amplifier has been analyzed. The analyses do not clearly reveal the role of CG stage in the cascode LNA, because the works mainly aimed at the linearization of the CG LNA used separately. The complete schematic of the 5.5 GHz LNA is shown in Figure 2.1, where Lg, Ls, and Ld are all implemented with on-chip spiral inductors. Lg is gate inductor and it is used for tuned out the effect of input capacitance and Ls is source degeneration inductor is used for input match and Ld is drain inductor provide output resonance with output capacitance and also play an important role to achieving high gain. The method employed here is inductive source degeneration. Cascoding transistor M2 issued to reduce the interaction of the tuned output with the tuned input, and to reduce the effect of the gate-drain capacitance Cgd of M1.the inductor Lc is used for interstage matching. At first, the sizes of the main CS FET and cg are selected considering the noise and bias current. The inductors Lg and Ls are chosen to provide the desired input resistance. M 3, R 1 and R 2 form a bias circuit. Transistor M 3 essentially forms a current mirror with M 1, here its width is a small fraction of the width of M 1 in order to minimize the power overhead of the bias circuit. The current mirror helps in temperature-stabilization of the circuit. The value of R 2 is adjusted to fix the operating point..cin and Cout are DC blocking capacitors. The load resistor Rd is tuned to manage the tradeoff between gain, output matching, and power

A low noise amplifier with improved linearity and high gain 1189 dissipation of LNA. In the schematic design the calculated width of M1 is 250um, and M2 is 170um and M3 is 25um, value of Ld is 1.7nH, supply voltage is 1.8V. 2.1 MATCHING NETWORK REALIZATION Matching network is important here because it allows maximum power transfer to occur from first stage to second. Signal-tonoise ratio will be improved simultaneously due to an increase in the signal level. The output reactance of common source mosfet and the input impedance of the common gate mosfet is- Figure 2.1: capacitive. Based on impedance matching theory, in order to maximize power transfer from M1 to M2. the input impedance of M2 should have a value equal to the complex conjugate of output impedance of M1. The inter-stage matching network can be realized by inserting a series inductor between M1 and M2.This series inductor Lc, together with the shunted c and composes of a match network which will give a good impedance matching between two MOSFETs and suppress signals of undesirable frequency as well as. 2.2 PROPOSED LNA CIRCUIT Figure 2.1: LNA 3. CONCEPT OF LINEARIZATION METHOD Due to the finite output impedance, the impedance increases and the nonlinear currents leak through the parasitic capacitance at the interstage node,which also appears at the output of the CG stage. This phenomenon is getting severe as the operating frequency and the load impedance increase. This explains why the CS linearized cascode LNAs have difficulties to achieve the high gain and high

IJECSE,Volume2, Number 4 Ram Kumar and Jitendra Mishra 1190 linearity simultaneously. However, the parasitic capacitances of degrades gain, linearity, and NF at high frequency Inserting inductor partially compensates this degradation. Thus, the proposed linearization technique is implemented on the cascode LNA. The inductor and the parasitic capacitances at the drain of and at the source of form a broadband network. Proper choice of cancels the capacitive effects. Under this condition, nonlinearity from can be neglected leaving as the dominant source of nonlinearity. The diode connected transistor M1a linearizes as follows. First, model the drain currents of M1 and M1a as + + 1 + + = (1) (2) (3) Where b1-b3 are in general frequency dependent and can be extracted from simulation [1]. In practice, the network cancels the effects of and at the frequency of interest. Since the currents at the drain node v2 of M1 have to satisfy the KCL equations, yielding the output current i2 = + + + 2 (4) Note that in the post distortion method, both the main and auxiliary transistors operate in saturation with the g1,2,3 same polarity. Hence, partially cancels the linear term as well.besides, the dc nonlinearity coefficients cannot capture memory effects in the transistors. To address these issues, the newly extracted Volterra coefficients are introduced. The output current ix can be re expressed as follows: +, +,, Where the extracted Volterra coefficients of g1; HB, g2; HB, and g3;hb are defined as the ratio of the ac current to the ac gate-tosource voltage at each output frequency. The subscripts HB indicate the coefficients are derived using Harmonic Balance (HB) simulation. It is observed that the proposed linearization technique can introduce the degree of freedom g2; Ma, HB and g3; Ma, HB, which partially cancels the second-order and third-order distortion terms. Though M1a partially cancels the linear term as well, it does not appreciably degrade the gain/nf because its bias is much less than that of M1. Thus, the proposed technique uses the diode Ma and resistor R to decide the magnitude and phase of second- and third-order nonlinearity contribution to IM3 product. To generate the ia, and choose the appropriate size of the diode and resistor for linearity optimization. The size of Ra affects the magnitude and phase of the composite second- and third-order nonlinearity contribution. Effects of the linearization technique on noise figure, The noise contribution from M1a is proportional to its transconductance(i.e gma) which is much smaller than gm1.thus,m1a does not significantly affect the noise figure (5) 5. EXPERIMENTAL RESULTS AND DISCUSSION The LNA under this study was simulated with a standard 0.18 um mixed-signal/rf CMOS technology provided by the UMC. The proposed LNAs consume only 10.8mW DC power With a supply voltage of 1.8 V. TABLE 1: Result Table S11 S12 S21 S22 NF IIP3 Power consumption -27dB -35dB 14dB -12dB 2.1dB 3.19dBm 10.8mw

A low noise amplifier with improved linearity and high gain 1191 Figure 4.1: S11 Figure 4.2: S12 Figure 4.3: S21

IJECSE,Volume2, Number 4 Ram Kumar and Jitendra Mishra 1192 Figure 4.4: S22 Figure 4.5: NF Figure 4.6: IIP3 5. CONCLUSION Based on the proposed linearization technique, a fully integrated 5.5 GHz CMOS LNA for high linearity applications has been demonstrated. The measured results of LNA with linearization circuit shows that it can improve linearity performance with small gain loss, noise figure and current consumption penalty and after simulation we got gain 14 db. NF 2.1dB, IIP3 3.19dBm and power consumption is 10.8mw. References [1]. X. Fan, E. Sánchez-Sinencio, and J. Silva-Martinez, A 3 GHz 10 GHz common gate ultrawideband low noise amplifier, in Proc. IEEE Midwest Symp. Circuits and Systems, Aug. 2005, pp. 631 634. [2]. T.-S. Kim and B.-S. Kim, Post-linearization of cascode CMOS LNA using folded PMOS IMD sinker, IEEE Microw. Wireless Comp. Lett., vol. 16, no. 4, pp. 182 184, Apr. 2006. [3]. N. Kim, V. Aparin, K. Barnett, and C. Persico, A cellular-band CDMA CMOS LNA linearized using active post-distortion, IEEE J.Solid-State Circuits, vol. 41, no. 7, pp. 1530 1534, Jul. 2006. [4]. H. Zhang, X. Fan, and E. Sánchez-Sinencio, A low-power, linearized,ultra-wideband LNA design technique, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 320 330, Feb. 2009. [5]. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [6]. S. Ganesan, E. Sánchez-Sinencio, and J. Silva-Martinez, A highly linear low noise amplifier, IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4079 4085, Dec. 2006. [7]. B. Razavi, RF Microelectronics. Prentice Hall, 1998. [8]. B. Kim, J.-S. Ko, and K. Lee, A new linearization technique for MOSFET RF amplifier using multiple gated transistors, IEEE Microwave and Guided Wave Letters, vol. 10, pp. 371 373, Sept 2000. [9]. T. W. Kim, B. Kim, and K. Lee, Highly linear RF CMOS amplifier and mixer adopting MOSFET transconductance linearization by multiple gated transistors, IEEE Radio Frequency Integrated Circuits Symposium, pp. 107 110, June 2003.

A low noise amplifier with improved linearity and high gain 1193 [10]. X. Fan, H. Zhang, and E. Sánchez-Sinencio, A noise reduction and linearity improvement technique for a differential cascode LNA, IEEEJ. Solid-State Circuits, vol. 43, no. 3, pp. 588 599, Mar. 2008. [11]. Zhang, C., D. Huang, and D. Lou, \Optimization of cascade CMOS low noise amplifier using interstage matching network,"proc. Electron. Devices and Solid State Circuit Conf., 465-468,Dec. 2003 [12]. Heng Zhang, Student Member, IEEE, and Edgar Sánchez-Sinencio, Life Fellow, IEEE linearization techniques for low noise amplifier:a tutorial. [13]. C.-P. Chang, W.-C. Chien, C.-C. Su, and Y.-H. Wang Linearity improvement of cascade cmos lna using a diode connected nmos transistor with parallel rc ckt.