Università degli Studi di Roma Tor Vergata Dipartimento di Ingegneria Elettronica Analogue Electronics Paolo Colantonio A.A. 2015-16
Field-effect transistors Field-effect transistors (FETs) are probably the simplest form of transistor, widely used in both analogue and digital applica>ons They are characterized by a very high input resistance and small physical size, and they can be used to form circuits with a low power consump>on They are widely used in Very Large-Scale Integra>on (VLSI) There are two basic forms: insulated gate FETs junc1on gate FETs Many forms, but basic opera>on is the same a voltage on a control input produces an electric field that affects the current between two other terminals when considering amplifiers we looked at a circuit using a control device a FET is a suitable control device 2 26
Field-effect transistors A FET is a suitable control device Vo = V I R The current I is controlled by the input signal Vi Thus the output signal Vo is controlled by the input signal Vi If an appropriate gain is given by the control device, it behaves like a voltage amplifier 3 26
Nota1on FETs are 3 terminal devices drain (d) source (s) gate (g) The gate is the control input Voltages are given symbols of the form V XX, where X and Y correspond to the symbols of two of the device s terminals (example V GS ) Currents are given symbols of the form I Z, where Z correspond to the device associated terminal (example I D ) Upper-case leters used for steady quan>>es V GS or I D Lower-case leters for varying quan>>es v gs or i d Special nota>on for power supply voltage or current, by doubling the subscript associated to the device terminal V DD, V SS, I DD, I SS 4 26
Insulated-gate field-effect transistors Such devices are some>mes called IGFETs (insulated-gate field-effect transistors) or some>mes MOSFETs (metal oxide semiconductor field-effect transistors) Digital circuits constructed using these devices are usually described as using MOS technology Here we will describe them as MOSFETs These devices are realized in either n-channel or p-channel semiconductor material 5 26
Insulated-gate field-effect transistors An n-channel device is formed by taking a p- type semiconductor (the substrate, namely bulk, b) and forming n-type regions within it to represent the drain and source pads Electrical connec>ons are made to these regions to form the drain and source electrodes A thin n-type channel is then formed to join these two regions (the channel) This channel is covered by an insula>ng oxide layer and then by a metal gate electrode Electrical connec>ons are made to the gate an substrate Usually the substrate is internally connected to the source to form a three terminal device (i.e. with only three external connec>ons) 6 26
MOSFET opera1on Gate voltage controls the thickness of the channel Consider an n-channel device making the gate more posi>ve atracts electrons to the gate and makes the channel thicker reducing the resistance of the channel. The channel is said to be enhanced making the gate more nega>ve repels electrons from the gate and makes the channel thinner increasing the resistance of the channel. The channel is said to be depleted 7 26
MOSFET symbols Devices as described above are termed deple>on-enhancement MOSFETs or simply DE MOSFETs Some MOSFETs are constructed so that in the absence of any gate voltage there is no channel Such devices can be operated in an enhancement mode, but not in a deple>on mode (since there is no channel to deplete) These are called Enhancement MOSFETs Both forms of MOSFET are available as either n-channel or p-channel devices 8 26
Junc1on-gate field-effect transistor Some>mes known as a JUGFET, most o`en with the common name JFET As in a MOSFET, conduc>on takes place through a channel formed in a semiconductor material Here the insulated gate of a MOSFET is replaced with a reverse-biased pn junc>on Since the gate junc>on is always reverse-biased no current flows into the gate and it acts as if it were insulated 9 26
JFET opera1on The reverse-biased gate junc>on produces a deple>on layer in the region of the channel The gate volt controls the thickness of the deple>on layer and hence the thickness of the channel Consider an n-channel device the gate will always be nega>ve with respect to the source to keep the junc>on between the gate and the channel reverse-biased making the gate more nega>ve increases the thickness of the deple>on layer, reducing the width of the channel increasing the resistance of the channel 10 26
JFET symbols The arrow shows the polarity of the device It points towards and n-type channel or away from in a p-type channel 11 26
FET characteris1cs While MOSFETs and JFETs operate in different ways, their characteris>cs are quite similar Input characteris1cs in both MOSFETs and JFETs the gate is effec>vely insulated from the remainder of the device Output characteris1cs consider n-channel devices usually the drain is more posi>ve than the source the drain voltage affects the thickness of the channel 12 26
MOSFET structre 13 26
MOSFET behaviour For V GS voltage below a minimum value (i.e. the threshold voltage V th ), the channel is not formed and there is no current flowing between drain and source 14 26
MOSFET behaviour For V GS above the threshold voltage V th, the channel is formed and there is a flux of charges (e - ) from S to D For small values of V DS the behavior is similar to a resistor 15 26
MOSFET behaviour The applied voltage V DS produces a drain current I D through the channel between the drain and the source Such a current produces a poten>al drop due to the channel resistance The poten>al gradually falls along the channel The thickness of the channel is mainly controlled by the voltage applied to the gate but it is also influenced by the drain-to-source voltage 16 26
FET output characteris1cs For small values of V DS, the behavior of the channel resembles that of a resistor, with the drain current I D being propor>onal to the drain voltage V DS The value of this effec>ve resistance is controlled by the gate voltage V GS It decreases as V GS is made more posi>ve This is referred as the ohmic region of the device s opera>on As V DS is increased the channel becomes more tapered and it thickness is reduced to approximately zero at the end near the channel The channel in this situa>on is said to be pinched off and the value of V DS is called pinch-off voltage This does not stop the flow of current, while preven>ng its any further increase This is referred to as the satura1on region of the device s opera>on 17 26
FET output characteris1cs If V GS is kept constant, while increasing V DS the current I D ini>ally rises (almost) linearly with the applied voltage (ohmic region) then above the pinch-off voltage becomes essen>ally constant (satura>on region) Varying V GS, the effec>ve resistance of the channel in the ohmic region and also the value of the steady current is changed 18 26
MOSFET output characteris1cs The DE MOSFETs are used with both posi>ve and nega>ve gate voltages, while MOSFETs use only one polarity (posi>ve V GS for n-channel type, NMOS, nega>ve for p-type, PMOS) The gate voltage at which the device starts to conduct is called threshold voltage V T For n-type DE MOSFET it will have a nega>ve value of a few volts For enhancement MOS a posi>ve value of a few volts ( at pinch off ) V = V V DS GS T I D [ma] 11 10 9 8 7 Locus of pinch-off V =V -V DS GS T V GS =+2 V V GS =+1 V Enhancement I D [ma] 11 10 9 8 7 Locus of pinch-off V =V -V DS GS T V GS =+9 V V GS =+8 V I DSS 6 5 4 3 2 1 0 5 10 15 20 25 V GS =0 V V GS =-1 V V GS =-2 V V GS =-3 V V GS =-4 V V GS =-5 V= V V [V] DS T Depletion 6 5 4 3 2 1 0 5 10 15 20 25 V GS =+7 V V GS =+6 V V GS =+5 V V GS =+4 V V GS =+3 V V GS V [V] DS =+2 V= V T 19 26
JFET output characteris1cs The output characteris>c of a JFET are similar to those of MOSFETs, except that the useful range of V GS is different The drain current produced for VGS=0 is termed the drain-to-source satura>on current IDSS The gate voltage at which the channel stops conduc>ng is now called pinch-off voltage V P I DSS I D [ma] 11 10 9 8 7 6 5 4 3 2 1 0 ( at pinch off ) V = V V DS GS P Locus of pinch-off V =V -V DS GS P 5 10 15 20 25 V GS =0 V V GS =-1 V V GS =-2 V V GS =-3 V V GS =-4 V V GS =-5 V V GS =-6 V VGS=-7 V= VP 20 26 V [V] DS
Transfer characteris1cs It represents the rela>onship between the input voltage V GS and the output current I D Obviously there is no linear rela>onship between V GS and I D However, if the device remains within the satura>on region, it is possible to plot such rela>onship Similar shape for all forms of FET but with a different offset I D I D I D DE NMOS NMOS JFET I DSS I DSS VT V GS VT V GS VP V GS ( ) 2 I = K V V D GS T I D V = IDSS 1 V GS P 2 Which can be rearranged into the form ( ) 2 I = K' V V D GS P 21 26
FET opera1ng ranges The rela>onship between the input voltage V GS and the output current I D does not show a linear response, but over a small region might be considered to approximate a linear response DE N-MOS N-MOS N-JFET When operating about its operating point the transfer characteristic can be described by its slope. This quantity has units of current/voltage, which is the reciprocal of resistance (that is conductance). It is called the transconductance, g m g m ΔI di i I = = ΔV dv v V D D d D GS GS gs GS 22 26
Early s voltage In a real FET, in the satura>on region the current I D slightly increase with V DS I D [ma] Locus of pinch-off V =V -V DS GS T V GS -1/λ V [V] DS The slope of the IV curve in the satura>on region represents a resistance r d Prolonging the characteris>c in the satura>on region towards le`, all of them cross in the same point at V DS =-1/λ, usually referred as Early s voltage Typical values of λ are between 0.01 and 0.03 V -1 2 ( ) ( 1 λ ) I = K V V + V D GS T DS 23 26
Small-signal equivalent circuit of a FET The transconductance g m is propor>onal to the square root of the drain current MOSFET did gm = = 2K ( VGS VT) = dv GS ( ) ID = 2K = 2 K I K D JFET did 2 V = = IDSS 1 dv V V 2 I I D DSS = IDSS = 2 VP I DSS V P The small signal equivalent circuit models the behaviour of the device for small varia>ons of the input about the opera>ng point g m GS GS P P I D r d is given by the slope of the output characteris>c and, for this reason, is also known as the output slope resistance 24 26
FETs at high frequencies At high frequencies more sophis>cated models are used The gate and the channel in a MOSFET are separated by an insulator, resembling a capacitor In a JFET, the insulator is replaced by a deple>on layer, which has the same effect In both case capacitances are present between the gate and the channel As the channel is joined to the drain at one end and to the source at the other, capacitance is present between the gate and each of the other terminals The reverse biased junc>on between drain and substrate also acts as a capacitor Since the substrate is normally joined to the source, it results in a capacitance between drain and source 25 26
FETs at high frequencies Considering the Miller effect 26 26