The Effect of Threshold Voltages on the Soft Error Rate - V Degalahal, N Rajaram, N Vijaykrishnan, Y Xie, MJ Irwin
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Soft Errors Soft errors or transient errors are circuit errors caused due to excess charge carriers induced primarily by external radiations These errors cause an upset event but the circuit it self is not damaged.
Soft Errors: Sources At ground level, there are three major contributors to Soft errors. Alpha particles emitted by decaying radioactive impurities in packaging and interconnect materials. Cosmic Ray induced neutrons cause errors due the charge induced due to Silicon Recoil Neutron induced 1 B fission which releases a Alpha particle and 7 Li
Soft Errors The Phenomena Current G A particle strike S D n+ n channel n+ + - + - + - +- + - + - + - + - + - p substrate B
Soft Errors The Phenomena VDD A particle strike Bit Flip!!! V in V out C L
Soft Errors For a soft error to occur at a specific node in a circuit, the collected charge Q at that particular node should be more then Q critical As CMOS device sizes decrease, the charge stored at each node decreases (due to lower nodal capacitance and lower supply voltages). This potentially leads to a much higher rate of soft errors
Soft Errors Soft Errors can cause problems in 3 different ways Affects the memory like Caches and Memory Affects the data path if the error propagates to the pipeline registers. Change the character of a SRAM-Based FGPA circuit.(firm Error)
Is it important? IRPS SER Panel Discussion April 2, 23
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Charge creation V t = V fb + V b + V ox where,v t is the threshold voltage, V fb is the flat band voltage, V b is the voltage drop across the depletion region at inversion, V ox stands for potential drop across the gate oxide By increasing the threshold voltage, we increase the energy required to push the electrons up the valence band
Logic attenuation under high V t Gain G is given by (1+r) G = ----------------------------- (V M -V T -V DSat /2)(λ n - λ p ) Where, r is switching threshold, V m is half of supply voltage, V dsat is drain saturation current, and λ n, λ p are channel length modulation factors for n-channel and p- channel
Logic attenuation under high V t 2.5 2 1.5 1 Low V th.5 High V th.5 1 1.5 2 2.5
Logic attenuation under high V t higher gain, hence a transient pulse will propagate in a system for a longer time and travels more logic stages. but the circuit will be slower!
Logic attenuation- Hazard Bubble 1 2 3 4 1 5 1 6 1 1 Clock Flip flop/ Latch Gate 6 Gate 5 Gate 4 Setup Hold Window of Vulnerability
Error Masking Logical masking : A particle strikes a portion of the combinational logic that doesn t determine output. Electrical masking : The pulse resulting from a particle strike is attenuated by subsequent logic gates. Latching-window masking : The pulse resulting from a particle strike reaches a latch, but not at the clock transition.
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Test Circuits and Methodology Used Flip-flops TGFF, C2MOS, SRAMS, 6inverter chain, FO4 Nand chains with FFs to latch errors. Layout in 7 nm BPT models, simulated in Hspice Transient Pulse modeled as current pulse with a sharp rise and slow decay Pulse only at nodes which produce change in output (No logic masking) Measuring metric: Q critical
Soft Errors SER _ Nflux * CS*exp (Q critical /Q s ) [Hazucha, 2] Nflux- Neutron Flux CS- Cross Sectional area Q critical Critical charge necessary for a Bit Flip Q s Charge Collection Efficiency Q critical = I d dt, Tf I d =Drain Current
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Results Qcritical (C) TGFF(1->) (LP) TGFF(->1) (LP) ASRAM (LP) 1.E-1 1.E-6 1.E-11 1.E-12 1.E-13 1.E-14 1.E-15 1.E-16 1.E-17 1.E-18 1.E-19 1.E-2 TGFF(1->) (Q) TGFF(->1) (Q) ASRAM (Q).1.2 Change in threshold voltages 1.E-7 1.E-8 1.E-9 1.E-1 1.E-11 Leakage Power (W)
Results Generally for Flip Flops & SRAMs Q critical increase with higher V t Q critical for ->1 higher then 1-> Leakage decreases with higher V t
Results- Q critcal _V th Q critical /C _V th Q critical /C 1.99E-2 4.75E-14 TGFF(1->).1.2 1.77E-19 3.87E-17 ASRAM.1.2 6.58E-14 7.58E-14 3.4E-2 1.28E-2 TGFF(->1).1 5.3E-2 Inverters.1 2.3E-2.2 4.18E-19.2 4.73E-2 Adder-1Bit(1- >).1.2 4.6E-2 1.35E-19 5.87E-17 Nand.1.2 2.23E-18 2.23E-18 5.24E-18 Adder-1Bit(- >1).1.2 3.67E-17 4.29E-17 7.13E-17 SRAM.1.2 4.75E-14 4.4E-14 3.82E-14
Results- Leakage Power _V th Leakage Power in W _ V th Leakage Power in W 1.18E-7 2.2E-7.1 3.42E-8.1 9.1E-9 TGFF(1->).2 3.4E-8 SRAM.2 3.42E-1 1.2E-7 2.2E-7.1 3.42E-8.1 4.9E-1 TGFF(->1).2 3.4E-8 ASRAM.2 1.99E-11 3.61E-5 2.56E-7 Adder-1Bit(1- >).1.2 3.49E-5 3.46E-5 Inverters.1.2 9.92E-9 4.9E-1 3.61E-5 2.4E-7 Adder-1Bit(- >1).1.2 3.49E-5 4.59E-6 Nand.1.2 9.66E-9 9.46E-1
Results at a glance Qcritical (C) TGFF(1->) (LP) TGFF(->1) (LP) ASRAM (LP) 1.E-1 1.E-6 1.E-11 1.E-12 1.E-13 1.E-14 1.E-15 1.E-16 1.E-17 1.E-18 1.E-19 1.E-2 TGFF(1->) (Q) TGFF(->1) (Q) ASRAM (Q).1.2 Change in threshold voltages 1.E-7 1.E-8 1.E-9 1.E-1 1.E-11 Leakage Power (W)
SRAMs Qcritical of 6-t SRAM changes a little Because of the regenerative nature the back to back inverters ASRAM, the Qcritical increases for the preferred state Due the difference in the driving strength of the PMOS or NMOS
Asymmetric SRAM VDD (Optimized for Leakage of ) The lower current drive of the high threshold voltage transistors make this design vulnerable to a stored value of 1(its non favorable state for leakage reduction). Similarly for the cell optimized for 1. [Azizi,Najm, 22 ] 1 Cell Leakage Bit line leakage
Flip Flops Flip flops evaluated for Most susceptible node Ability to latch the transient pulse Two factors gain of the inverter- should decrease Q critical Transmission gate present at the slave - should increase Q critical
Flip Flops _Vth Q critical at input/c Q critical at most susceptible node/c 6.6E-21 1.24E-2 SDFF.1 5.8E-21 1.33E-2.2 - - 3.69E-2 7.12E-21 C 2 MOSFF.1 5.64E-2 7.17E-21.2 1.68E-19 1.99E-2 7.36E-21 TGFF.1 1.77E-19 7.36E-21.2 3.87E-17 7.36E-21
Flip Flops TGFF!clk clk Both factors cancel out, hence Q critical almost same at most susceptible node D S Qm Q At the input D, the presence of the transmission gate results in a large increase in Q critical clk TGFF!clk
Flip Flops C 2 MOS no inverter in the path to the output Q critical increases for both the nodes S and D D clk!clk S!clk clk!clk clk clk!clk Q B. C 2 MOS-FF
Flip Flops SDFF few sized devices resulting in a much higher Q critical for node X With high Vt, at input the greater overlap time is actually going to help pull down the value X more and hence reduces the Q critical D X clk B. SDFF Q
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation Methodology Flip-Flops, SRAM Logic chain- Inverter & Nands Results Flip-flops SRAMs Combinational logic
Results- Q critical 14 12 Relative Qcritical 1 8 6 4 2 TGFF(->1) SRAM Adder-1Bit(->1) ASRAM _V th =.1 _V th =.2 Inverters Nand
Logic Chains Q critical depends on the output flips flop High V t FF, Qcritcal increases Low V t FF, Qcritcal decreases Qcritical/C 5E-2 4E-2 3E-2 2E-2 1E-2 6 inverter chain with TGFF at out put. High Vt-FF Low Vt-FF.1.2 Threshold Voltages
Delay Balancing Practice to use high V t on fast path to do delay balance Effects the hazard bubble Use 6/3 invert chains for slow/fast logic R E G I S T E R S Slow Path Fast Path R E G I S T E R S
Delay Balancing 1.6E-2 1.4E-2 Qcritical of fast paths reduces Qcritical (C) 1.2E-2 1E-2 8E-21 6E-21 4E-21 2E-21 Use High V t flip flops Low V th + Low V th FF Slow path ( 6 inverters) Low V th + Low V th FF High V th Low V th FF Fast Path (3 inverters) High V th + High V th FF
Conclusion Certain designs (like TGFF) have higher Q critical for high V t, others (like static logic chains) have lower Q critical. ASRAM has lower leakage and higher Q critical Delay balancing can potentially increase SER, can use high-vt TGFF to buy back the Q critical. Analysis of leakage reduction strategies on SER is critical