September 2, 2004 Motorola PRF5P21240 RF Power MOSFET Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures and Tables 1.2 Introduction 1.3 Major Findings 2 Device Overview 2.1 Package and Die 2.2 MOSFET Die Features 3 Process Analysis 3.1 General 3.2 Die Edge and Die Corners 3.3 Bond Pads 3.4 Passivation 3.5 Inter-metal Dielectrics (IMD) and Pre-metal Dielectric (PMD) 3.6 Metallization 3.7 Contacts and Vias 3.8 MOS Transistors and Polysilicon 3.9 Isolation 3.10 Wells and Epi 3.11 Output Capacitor 4 Materials Analysis 4.1 SIMS Analysis 4.2 SRP Analysis 4.3 EDS Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions Report Evaluation Rev 1.0 - Feb 27, 2004 04:59 \\edge\projwork\reports\_templates\sar_pagemaker\manufacturer\device_no\sar\sar-code.vsd
Overview 1 Overview 1.1 List of Figures and Tables 2.1.1 Top and Bottom Package Photographs 2.1.2 Package Cavity Photograph 2.1.3 Die #3 - Power MOSFET Die 2.1.4 Die #1 - Interconnect Die 2.1.5 Die #2 - Output Capacitor Die 2.1.6 Die #4 - Interconnect Die 2.1.7 Die Label for Interconnect Die #1 2.1.8 Die Label for Capacitor Die #2 2.1.9 Die Label for Interconnect Die #4 2.2.1 Power MOSFET Die Corner 2.2.2 Power MOSFET Die Corner 2.2.3 Power MOSFET Die Corner 2.2.4 Power MOSFET Die Corner 2.2.5 Bond Pad Optical Micrograph 2.2.6 FESEM Image of Wire Bonding to Power MOSFET Chip 2.2.7 ESD Protection Structure 3.1.1 Top View Optical Microscopy Image of Transistor Array 3.1.2 General View of MOSFET Device Structure 3.2.1 FESEM Image of Die Corner 3.2.2 Die Edge Cross-Section 3.2.3 Die Edge Seal Cross-Section 3.3.1 Bond Pad Cross-Section Outer Edge 3.3.2 Bond Pad Cross-Section Inner Edge 3.3.3 Wire Bond Cross-Section 3.3.4 Detail of Wire Bond Cross-Section 3.4.1 Top View of Passivation 3.4.2 Passivation Cross-Section 3.5.1 Inter-metal Dielectric 3.5.2 Pre-metal Dielectric 3.6.1 Minimum Dimension Metal 2 3.6.2 Minimum Dimension Metal 1 3.6.3 Metal 0 Dimension 3.6.4 Metallization Composition and Thickness 3.7.1 Cross-Section Through Metal 1 Contact 3.7.2 Cross-Section Through Metal 1 to Metal 2 Via 1-1 Rev 1.0 - April 5, 2004 08:03 \\edge\projwork\reports\motorola\prf5p21240\sar\sar-0404-006.vsd
Overview 3.8.1 Transistor Cross-Section Perpendicular to Array Showing Source and Drain Contacts 3.8.2 Perpendicular Cross-Section Showing Transistor Shield Connection to Source 3.8.3 Transistor Cross-Section Showing Gate Contact 3.8.4 Transistor Gate and Drift Region 3.8.5 Transistor Gate Contact Detail 3.8.6 Detail of Source Contact 3.8.7 Minimum Spaced Polysilicon in ESD Structure 3.9.1 Bird s Beak in Recessed LOCOS Showing Gate Poly 3.9.2 Bird s Beak in Recessed LOCOS Between Gates 3.10.1 Optical Micrograph of P-well 3.10.2 Scanning Capacitance Microscopy Image of Transistor Structure 3.10.3 Scanning Capacitance Microscopy Image Showing Transistor Gate Region 3.11.1 Cross-Section of Output Capacitor Metallization 4.1.1 FESEM Cross-Section Through Dielectrics 4.1.2 SIMS Profile of Dielectric Layers 4.2.1 Spreading Resistance Profile Showing P-Well and Graded P-epi on P-substrate 4.3.1 EDS Spectrum of Bonding Wire 4.3.2 EDS Spectrum of Bond Pad 4.3.3 EDS Spectrum of Metal 2 4.3.4 EDS Spectrum of Metal 1 4.3.5 EDS Spectrum of Metal 1 Barrier 4.3.6 EDS Spectrum of Gate Silcide 4.3.7 EDS Spectrum of Gate Shield 1-2 Rev 1.0 - April 5, 2004 08:03 \\edge\projwork\reports\motorola\prf5p21240\sar\sar-0404-006.vsd
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