Sensor-Element Organization 00 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Low Noise for Gray-Scale Applications Output Referenced to Ground Low Image Lag... 0.% Typ Operation to MHz Single -V Supply description The TSL0 linear sensor array consists of two sections of photodiodes each and associated charge amplifier circuitry, aligned to form a contiguous pixel array. The device incorporates a pixel data-hold function that provides simultaneous integration start and stop times for all pixels. The pixels measure. µm by. µm, with.-µm center-to-center spacing and -µm spacing between pixels. Operation is simplified by internal logic requiring only a serial-input pulse (SI) and a clock. The TSL0 is intended for use in a wide variety of applications including mark and code reading, OCR and contact imaging, edge detection and positioning, and optical encoding. SI AO SO VPP functional block diagram (each section pin numbers apply to section ) (TOP VIEW) 0 SO SI AO No internal connection Pixel + _ Sample/Hold/ Output Integrator Reset Pixel Pixel Pixel Analog Bus Output Amplifier AO R L (External Load) Switch Control Logic Gain Trim Hold Q Q Q Q SO SI -Bit Shift Register
TERMINAL NAME NO. AO Analog output of section AO Analog output of section Terminal Functions DESCRIPTION Clock. Clk controls charge transfer, pixel output, and reset., Ground (substrate). All voltages are referenced to.,, No internal connection SI Serial input (section ). SI defines the start of the data-out sequence for section. SI 0 Serial input (section ). SI defines the start of the data-out sequence for section. SO Serial output (section ). SO provides a signal to drive the SI input (in serial connection). SO Serial output (section ). SO provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. Supply voltage. Supply voltage for both analog and digital circuitry. VPP Connected to detailed description device operation (assumes serial connection) The sensor consists of photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent, which is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The output and reset of the integrators is controlled by a -bit shift register and reset logic. An output cycle is initiated by clocking in a logic on SI. An internal signal, called Hold, is generated from the rising edge of SI and simultaneously transmitted to sections and. This causes all sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first clock cycles, all pixel integrators are reset, and the next integration cycle begins on the th clock. On the th clock rising edge, the SI pulse is clocked out on the SO pin (section ) and becomes the SI pulse for section (SI). The rising edge of the th clock cycle terminates the SO pulse, and returns the analog output AO of section to high-impedance state. Analog output AO now becomes the active output. As in section, SO is clocked out on the th clock pulse. Note that a th clock pulse is needed to terminate the SO pulse and return AO to the high-impedance state. AO is driven by a source follower that requires an external pulldown resistor. When AO is not in the output phase, it is in a high-impedance state. The output is nominally 0 V for no light input and V for a nominal white level output, with a nominal full scale (saturation) voltage of V. The TSL0 can be connected in the serial mode, where it takes clocks to read out all pixels, or in the parallel mode where it takes clocks to read out all pixels (see application section).
absolute maximum ratings Supply voltage,......................................................................... V Digital output voltage range, V O............................................... 0. V to + 0. V Digital output current range, I O................................................... 0 ma to 0 ma Digital input current range, I I..................................................... 0 ma to 0 ma Operating free-air temperature range, T A............................................... 0 C to 0 C Storage temperature range, T stg.................................................... C to C Lead temperature, mm (/ inch) from case for 0 seconds............................... 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see Figure and Figure ) MIN NOM MAX UNIT Supply voltage,.. V Input voltage, V I 0 V High-level input voltage, V IH 0. V Low-level input voltage, V IL 0 0. V Wavelength of light source, λ 00 000 nm Clock frequency, f clock 000 khz Serial connection 0. 00 Sensor integration time, t int Parallel connection 0.0 00 Setup time, Serial input, t su(si) 0 ns Hold time, serial input, t h(si) (see Note ) 0 ns Operating free-air temperature, T A 0 0 C NOTE : SI must go low before the rising edge of the next clock pulse. ms SI Internal Reset Clock Cycles Integration Not Integrating Integrating AO Clock Cycles ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Hi-Z Hi-Z Figure. Timing Waveforms (Serial Connection)
electrical characteristics at f clock = 00 khz, = V, T A = C, λ p = nm, t int = ms, R L = 0 Ω, E e = µw/cm (unless otherwise noted) (see Note ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog output voltage (white, average over pixels).. V Analog output voltage (dark, average over pixels) E e = 0 0 0. 0. V PRNU Pixel response nonuniformity See Note ±0% Nonlinearity of analog output voltage See Note ±0.% Output noise voltage E e = 0, See Note mvrms Saturation exposure See Note.. nj/cm Analog output saturation voltage. V DSNU Dark signal nonuniformity All pixels, E e = 0, See Note 0.0 0. V IL Image lag See Note 0.% I DD Supply current R L = 0 Ω ma I IH High-level input current V I = 0 µa I IL Low-level input current V I = 0 0 µa C i Input capacitance 0 pf NOTES:. Clock duty cycle is assumed to be 0%.. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated.. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white).. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a -second period.. Saturation exposure is calculated using the maximum responsivity and minimum output saturation voltage figures.. DNSU is the difference between the maximum and minimum of dark-current voltage.. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: V V AO AO(dark) IL 00 V V AO(white) AO(dark)
operating characteristics over recommended ranges of supply voltage and operating free-air temperature unless otherwise noted (see Figure ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t pd(so) Propagation delay time, SO, SO 0 ns t w Clock high or low 0 ns t s Analog output settling time to ±% R L = 0 Ω, C L = 0 pf 0 ns t w () () V 0 V SI t su(si) 0% t h(si) V 0 V t pd(so) t pd(so) SO t s t s AO Pixel () Pixel () Figure. Operational Waveforms (each section)
APPLICATION INFORMATION 0. µf SI SI AO SO VPP SO SI AO 0 AO R L Cycles Cycles ÎÎÎÎÎÎÎÎÎ t int + clocks SI SO, SI AO Common ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ AO ( ) AO ( ) Figure. Serial Connection
APPLICATION INFORMATION Si AO (pixels ) 0. µf R L SI AO SO VPP SO SI AO 0 AO (Pixels ) R L SI (SI, SI) SO, SO Cycles ÎÎÎÎÎÎÎÎÎÎÎÎ t int + clocks AO ÎÎÎÎÎÎÎ A0 ( ) ÎÎÎ AO A0 ( ) Figure. Parallel Connection
TYPICAL CHARACTERISTICS PHOTODIODE SPECTRAL RESPONSIVITY T A = C 0. Normalized Responsivity 0. 0. 0. 0 00 00 00 00 00 00 00 000 λ Wavelength nm Figure 00
MECHANICAL INFORMATION This assembly consists of a sensor chip mounted on a printed-circuit board in a clear molded plastic package. The distance between the top surface of the package and the surface of the sensor is nominally mm (0.00 inch). 0, (0.0), (0.0) C L, (0.0) MAX Both Rows Bottom View 0, (0.0) NOM First Pixel Location,0 (0.0), (0.0), (0.0) MAX Places 0, (0.00) T.P. Places (see Note C),(0.),(0.0) Sensor Center Line,(0.),(0.), (0.), (0.0) C L L C, (0.0), (0.0) Seating Plane 0,(0.0) 0,(0.0), (0.0) MIN 0,0 (0.00) 0,0 (0.0) Diameter All Pins NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The true-position spacing is, mm (0.00 inch) between lead centerlines. Each pin centerline is located within 0, mm (0.00 inch) of its true longitudinal positions. D. Index of refraction of mold compound =. E. Designation per JEDEC Std. 0: PDIP-T Figure. Clear Molded Plastic Package