Static Noise Analysis Methods and Algorithms Final Survey Project Report 201C: Modeling of VLSI Circuits & Systems Amarnath Kasibhatla UID: 403662580 UCLA EE Department Email: amar@ee.ucla.edu
Table of Contents 1. Introduction. 3 2. Noise Margin Criteria. 4 3. Harmony: Static Noise Analysis Method.. 6 3.1 Macro Level 7 3.2 Global Level.. 10 4. Aggressor Alignment for worst case noise..12 5. Static Noise Analysis with Timing Windows.. 14 6. Non-linear superposition of noise sources. 16 7. Conclusions.. 18 8. References 18
1. Introduction Static Noise analysis is becoming increasingly important in the Sub-Micron era due to the potential functional failures that can result in static-noise-unchecked design and is now a metric in the design performance. Static Noise Analysis is a step in standard flow of digital integrated circuits. Static Noise can cause functional failures in different ways but all of them resulting due to data being corrupted at any of the static, dynamic nodes and even nodes with feedback. Noise margin is defined in a generic way as the amount of deviation of the input from the ideal logic HIGH or LOW values and still resulting in correct and valid output logic levels. Binary digital logic propagates through a network of logic gates in the form of two voltage levels corresponding to HIGH and LOW logic states. The nodes holding these voltages can be static, dynamic or regenerative. Any amount of noise that can be injected into these nodes without actually corrupting the correct data is called the noise margin of that node. There are various mechanisms that could induce noise onto the output node. Noise can propagate from the input to output when the input logic value is different from the ideal value and results in an output value different than ideal output value. This in turn propagates. This phenomenon is called Propagated Noise.This is illustrated in the below figure. The next way that noise could affect a node is through Capacitive Coupling as shown below. The parasitic coupling capacitance associated with interconnects induces noise on to the
neighboring nets disturbing their stable voltage levels. The time for which the coupling noise sustains depends on the values of coupling and self capacitances as well as the effective resistance of the transistors that strive to maintain the voltage of the node. The third common form of noise induction is through Charge Sharing. This is illustrated in the below Figure 3. The leakage currents can cause the charge on the output nodes to discharge into the internal nodes of the transistor stack. This happens especially in Dynamic logic where the charge at the output is vulnerable to both leakage as well as the input vector that turns on transistors in the stack. This is not considered serious because Dynamic logic circuits are generally designed with a keeper that will pull back the output voltage to the nominal level, but this can be a serious impediment in circuits with high leakage currents. Another way noise that can be induced on to the output as well as onto the input nodes is through capacitive feedback. This is shown in Figure 4. Inputs that share gate-drain capacitances with output nodes can actually directly couple the input value to the output resulting in overshoots and undershoots at the outputs. This sort of effect can actually inject noise onto other inputs in neighboring transistors through capacitive feedback. 2. Noise Margin Criteria One traditionally analyzes noise in analog circuits by adding noise generators for each possible physical noise source to the complete small-signal equivalent circuit. These noise generators are usually in the form of mean-square voltages or currents. By contrast, the highly nonlinear operation of digital circuits and the more deterministic nature of man-made noise sources requires an entirely different kind of analysis and verification metric. To guarantee that a digital integrated circuit will function, we must verify that latching structures that hold state do not falsely switch in the presence of noise. The act of switching a latch defined by a positivefeedback configuration of restoring logic gates involves making the circuit unstable. Therefore, we refer to the requirement that a latch not be driven unstable by noise as the essential
stability requirement. Essential stability is the necessary and sufficient condition for the functionality of a digital circuit. This is illustrated the below Figure 5. Let and be the voltages on nodes and, respectively. and are the transfer functions of gates I and II ie, y = f(x) and x = g(y). The latch will be stable in the presence of the series-voltage dc noise sources A and B on the evaluation nodes A and B, if the following equations hold at the bias point determined by these sources, as per [1], If the above condition is applied to every restoring logic gate in the circuit, it is never possible for any positive feedback configuration to switch in the presence of dc noise. This is the ondition which is traditionally used to define the worst case static noise margins (or simply static noise margins). The DC Noise margin defined by the above criteria is however much pessimistic and conservative to be applied for pulse noise sources such as those that of charge sharing or capacitive coupling because they fail to consider the fact that logic gates act as low pass filters. Pulse-noise amplitudes are allowed to be higher than static noise margins would allow, depending on the shape of the pulse. These dynamic noise margins are dependent on the time domain characteristics of the pulse noise. This can be illustrated using the circuit in Figure 6,
In the feedback circuit of Figure 6 a noise source is injected at the input A. The latch is initially in the state in which node is low and node is high with a 2.5- V supply. Figure 7 (a) shows the behavior of the latch when the peak noise amplitude of the injected noise is 1.37V and 1.38V. For 1.37 V, the noise is tolerated and for 1.38V the noise will corrupt the node voltages A and B. So according to this the noise margin is seen as 1.37V. However if we look at the 7(b), which shows the input and output waveforms and the time domain DC sensitivity, the noise corrupts the latch even if the input is 1.1 V. So according to the conventional definition, the noise margin is 1.1 V whereas the experiment for Figure 7(a) says that the circuit can tolerate up to 1.37 V noise. The fact that the latch can actually tolerate an additional 280 mv of pulse noise before switching is indicative of the conservatism in the noise stability approach. Because gate II is subunity-biased, more noise can be tolerated on gate I. This margin is not significant in practice for bistable latch circuits because once a restoring logic gate is biased by noise beyond the unity-sensitivity threshold, the magnitude of the sensitivity rapidly increases. The main source of conservatism in the noise-stability metric comes in applying this test at every restoring logic gate rather than only at latches. In a more generic manner the noise margin throughout this report uses this definition Every restoring logic gate, when acted upon by a noise stimulus, must have a time-domain dc-noise sensitivity that is always less than one. 3. Harmony: Static Noise Analysis Method Harmony is a two-level hierarchical noise analysis method proposed in [2]. The first level called Macro level performs noise analysis on a group of digital gates which are connected. In each Macro, at the Macro level, the method constructs graphs for all digital circuits for which noise analysis is done. The second level which is called Global level treats individual Macros as modules which are connected by interconnects and performs noise analysis globally.
3.1 MACRO level: For illustration consider the below digital circuit, which contains typical elements of a digital circuit path. Macro level method constructs a noise graph corresponding to the above circuit. There are three types of segments in a noise graph: restoring segments, propagate segments, and node-injection segments. Restoring segments cross gates that at some dc bias point have a small-signal gain greater than one. Noise is propagated across restoring segments; in addition, a noise stability check must also be performed. Propagate segments [e.g., the dashed line joining nodes and in Fig. 9] connect nodes, between which there is sub-unity gain at all dc bias points. Noise-stability checking is not required across propagate segments. Each restoring and propagate segment in the noise graph is labeled by the type of noise propagated by the segment. For example indicates that the segment propagates V L noise and transforms it into V H noise. The node-injection segments (dashed lines in Fig. 9 that are not sourced by nodes) can introduce noise directly onto an evaluation node, superposing with the propagated noise. Coupled interconnect noise, denoted by (C), and charge-sharing noise, denoted by (CS), are both modeled as node-injection segments. Once the noise graph is constructed, the loops of the graph are broken and the graph is topologically sorted for traversal.
The analysis of each node involves calculating, through transistor-level simulations, the noise appearing at each CCC output and verifying the stability of the noise waveforms appearing at each input. The noise calculation begins by establishing the dc voltages (or base levels) associated with logic high and logic low. These can differ from the rails by a threshold-voltage drop in the case of noncomplementary pass gates, for example. As part of this analysis, input combinations that cause the output of a node, O, to float (have no path to V DD or ground) or collide (have paths to both V DD and ground) are also examined. Both conditions should be reportable to the user since they sometimes represent unintended circuit behavior. Collision cases must be individually verified to determine if they unambiguously resolve to a logic high or logic low (e.g., ratioed logic has valid ratioing). In the case of floating nodes, a dc base level must be asserted at the output as an initial value (e.g., as might result from a previous phase precharge level). Subthreshold leakage in the case of dynamic or weakly-static nodes must also be considered as part of the dc base-level analysis. This leakage is allowed to act for a clockperiod-dependent period of time to determine the final degraded base level. Having established the base levels of logic high and low, we now consider the possible ways noise can upset this voltage, beginning with coupled noise. We define a path function f Pi,j as the logical condition for the channel path from to conduct. To sensitize for noise appearing on O due to capacitive coupling to a given node, D, in the CCC, we establish logic constraint relations depending on the type of noise propagating from D to O. In particular, let us consider the sensitizations that allow V L noise to appear on O due to capacitive coupling to D. In this case, the V L noise at O is produced by a perpetrator net switching from ground to V DD. There are two possible constraint relations. The first is as below, that allows V L noise on D to propagate to O. The second is below, that allows V H noise on D to propagate to O. Note that these sensitization conditions explicitly check that a transition on the output will not be produced by the full transition of the target input. Also note that the input constraints are smoothed with respect to the switching input since the switching input does not have to satisfy static logic constraints. In the example of Figure 8, if the NAND gate is very skewed in favor of the pulldown, then V H charge-sharing noise can be introduced at O. by the switching of input from low to high. In this case, and are one, while and are zero. This corresponds to sensitization 11 in Table I. These sensitizations can be obtained using Boolean Satisfiability method. Now the noise onto the node O due to propagation of input noise becomes the worst value from all the sensitizations from Table I. Similarly the sensitizations for Charge-sharing noise onto node O are obtained and hence the worst case noise at the node O. In general, to find the noise appearing at the output of a given node, we must find the combined sensitization producing the largest amplitude output noise for each noise type (VL or V H ).
In addition two types of constraints on the switching signals can be used to further limit noise combinations. Hazard-Free Logic Constraints: These are logic constraints that apply to signals that are known to be hazard-free. For example, if two hazard-free signals are complementary, then a rising transition on one implies a single falling transition on the other. Timing Orthogonality: If two signals cannot switch together as a result of static timing analysis, then the simultaneity of these two switching events is precluded in combining noise sources. At the Global level, the individual Macro level noise analysis reports are taken and stitched with the RC interconnect network to perform Global Level Noise analysis. For that purpose, the input and output nodes of the digital circuit groups analyzed at the Macro level are modeled as ports as show in Figure 10 with different behavior for static and dynamic conditions. Noise-inputs are pins through which noise can be injected; noise-outputs are pins from which noise can be propagated; while noise-bidis can function as both noise-inputs and noise-outputs. Ports of the network must be modeled in two ways, statically to determine how the ports act to
hold nets quiet in the presence of noise and dynamically to determine the noise that is propagating in on the given pin or that can be tolerated on a given pin. The static model for an input port, as shown in Figure 10, describes how the port acts to hold a net quiet R H and R L are the node impedances, the effective pull-up and pull-down resistances controlled by the variables H and L, which participate in sensitization along with other input variables. In most cases, H and L are constrained to be mutually exclusive, which precludes floating node and collision conditions. For an output pin, the static model is a capacitor as shown in Figure 10. The dynamic model for noise-input pins consists of a piece-wise-linear voltage source connected to the pin. Noise-outputs can have a dynamic model characterized by a dc noise margin check. 3.2 Global Level Once Macro Harmony has been used to analyze each macro block, we must consider all the long interconnect of the chip. The Global Harmony engine is nothing more than a detailed coupled noise calculator, since all the transistorlevel analysis is done and abstracted by Macro Harmony. Interconnect resistance is included in the Global Harmony interconnect analysis. In addition, timing information becomes very important in reducing pessimism, since most of the coupled noise is introduced in the global wires connecting the macros. This global detailed timing information is also available in the design methodology in which Global Harmony is employed. The reduced-order modeling approach employed in Global Harmony guarantees passive, multiport macromodels with symmetry that allows for efficient storage of the results. Multiport models are used so that the interconnect models remain independent of changes in the macro driver strengths and input pin capacitances. These macromodels are also employed in the static timing analysis of the same design. The first step in the reduction process is to identify a net complex for each global net in the design. The primary net of the complex is the net on which we are trying to calculate the noise; that is, the net which should be statically quiet. The complex also includes secondary nets of significant coupling to the primary net. To determine which secondary nets to include in a complex, we calculate the ratio for each secondary net, where is the total coupling capacitance to the given secondary net and is the self capacitance of the primary net in the complex. Secondary nets for which this ratio is below a designated threshold are discarded. Modified nodal analysis (MNA) is used to stamp conductance and capacitance matrices according to the multiinput, multioutput, linear time-invariant differential equations x,v and i are the state, output voltage, and input current vectors, respectively. For a system with n nodes and r ports G and C are the symmetric, positive semidefinite conductance, and capacitance matrices, respectively. The state vector is ordered so that the first elements represent the port voltages. Moving into the Laplace domain, led to an expression for the -by- multiport impedance matrix for the net complex The noise abstracts generated from the Macro Harmony run are used along with the interconnect macromodels to check the noise on the global interconnect. First driver resistance and receiver
capacitances are folded from the abstract port modeling for the primary net into the multiport impedance as shown in Figure 11. It is assumed that the superposition principle applies for calculating the effective noise at a node. The problem can be formally stated as follows. Let c i be the peak noise on a given primary receiver associated with driver i.. Let t i early be the earliest arrival time associated with secondary driver and let t i late be the latest arrival time associated with secondary driver i. let τ i be the switching time associated with secondary net driver I, such that all the noise peaks align for the primary receiver in question. Let x i be the binary variable indicating whether the given secondary net driver is switching, and let be the number of secondary nets. The problem is then to maximize such that the following constraints can be satisfied for all : where is a continuous variable determining the absolute time reference for the τ i. This formulation assumes a certain sharpness to the noise peaks. When the peak falls outside the arrival-time window, its contribution is taken as zero. Brand and bound is utilized to solve this problem since the noise on each subtree can be easily bounded by the assumption that each node in that subtree is contributing. Effectively the noise propagated is added to the noise from the receivers and an overall noise-slack report is generated.
4. Aggressor Alignment for Worst Case Noise The third paper [3] proposes a technique that aligns aggressor coupling noise effects to estimate the worst case output noise more accurately. The important contributions of this paper in terms of improvement over HARMONY [2] are as below: 1. The assumption in HARMONY that the worst case noise is the sum of individual noises aligned in time domain does not necessarily lead to Worst Case Noise. (WCN) 2. The simple linear Thevenin model of HARMONY is inaccurate for large values of noise, because transistors are no longer in triode region. These models are replaced by a slightly better PWL version. 3. HARMONY assumption that excludes contribution of aggressors whose noise peaks are not within timing window is inaccurate for large pulse widths. Capacitive coupling effects depend on the characteristics of drivers, interconnects and receivers. Interconnect coupling network consists of resistors and capacitors. The receiver functions as a loading capacitor. All the above mentioned elements are linear, except for the victim driver whose modeling will be discussed below. When the noise amplitude resulting from switching of all the acting aggressors is small, the quiet victim driver works in its linear region, so it can also be treated as a linear element. Therefore, superposition should be applicable for coupling induced noise in such a case. However, with stronger coupling, noise is no longer small. Thus the assumption that the victim s driver is in its linear range may not be true. The summation of individual peak noises may not result in an upper bound for coupling noise. Figure 12 shows the inaccuracies that result due to traditional aggressor alignment. Figure 12(c) and (d) show that the output noises due to individual aggressors align with each other when aggressor input arrivals are skewed with respect to each other. So this actually generates a sweep line (the dotted line) as shown in (c) that represents the relative skew requirement for WCN. Now this analysis is done assuming that the aggressor input values
arrivals have no restrictions on them. When the real arrival window times of the aggressors are known, the sweep line can be used to find out the agressors that actually contribute to the output node as shown in the below Figure 13. So now, only agressors A1, A2 and A5 which actually overlap with the sweep line contribute to the noise at the output and the effective noise at the output will be their sum. Aggressor Alignment with timing constraints requires Effective Pulse Width (EPW) calculation. EPW is a measure of the range of a noise waveform. Given v 0 (t) as noise output, its EPW is defined as follows:
Through simulation, it was found that the width of the noise pulse cannot be neglected (several hundred pico-second is not an unusual value), and the actual shape of noise pulse is not always sharp at its top. Therefore, partial contribution (when the peak noise is not aligned) of each coupling noise which has been ignored in [2] should still be considered. Aggressor alignment 2 can be re-formulated as shown in figure 14. Figure 14(a) shows the original timing window and sweep line. In figure 14(b), the sweep line has been straightened. Consequently, the timing windows have been moved and satisfy the following condition: A line sweep in (a) is equivalent to that of (b), in terms of vertical intersections with particular aggressor windows. In figure 14(c), timing window has been expanded to include the width of the noise pulse. The total expanded portion for each timing window is the corresponding pulse width EPW. Now with a set of adjusted and expanded timing windows, as well as an imaginary straightened sweep line, we re-formulate the aggressor alignment problem as a Weighted Channel Density problem which calculates maximum number of segments intersecting a vertical line. Our weighted channel density algorithm finds the location for maximum vertical channel density with segments weighted. It is a direct extension of the original channel density algorithm and is not list it here. The location information will be used to decide the switching aggressors involved in maximum noise as well as their corresponding arrival times. 5. Static Noise Analysis with Timing Windows The fourth paper [4] proposes a technique that allows more accurate estimation of noise through noise window propagation instead of absolute worst case noise through a signal path. The key contributions of this paper are: a) The timing of the injected noise is considered before propagating it to the next stage. b) Timing of the injected noise should be aligned with the clock s setup and hold window before flagging the noise as a violation that corrupts the latch data. c) Finally, the timing window of the noise instead of just the DC worst case noise is propagated to more accurately estimating the worst case noise and reduces false violations. Conceptually, noise glitches propagate through logic gates just as switching signals propagate through logic gates. So, just like Static Timing Analysis, Static noise analysis also can calculate the early and late arrival times of noise in every net. The early and late arrival times at register inputs are checked against the clock arrival time T CK and the setup and hold times to determine timing violation. In Figure 15, nets a1 and a2 are aggressors to nets 1 and 2 respectively. [t a1e,t a1l ] defines the early and late arrival times, or timing windows, of aggressor net a1. When a1 switches, a noise glitch is created on net 1 at time tda1 delay from the switching point of a1 to the gate input of net 1. The peak magnitude of the noise on net 1 is represented by v1. Hence, the noise window on net 1 is represented by the triplet [t 1E,t 1L,v 1 ]. A similar calculation is performed on net 2. Next we calculate the noise window on net 3. In essence we need to calculate the output noise waveform and the propagation delay from input noise peak to
output noise peak. The propagation delay is represented by t D13 and t D23. The output noise magnitude from input noises at net 1 and net 2 are represented by v 13 and v 23 respectively. The noise window at net 3 is the union of the noise window on net 3 contributed by net 1, and the noise window on net 3 contributed by net 2. Finally, when a noise window reaches a register input, the intersection of the noise window and the register s sensitive window forms the effective noise window [t 3E,t 3L,v 3 ]. The worst case noise waveform within the effective noise window is used as propagated noise input to the register to determine noise immunity. As an example, the circuit in Figure 16 shows various sources of noise and how they are propagated down the digital path.
This analysis shows that the final value of D which sees the injected noises from various sources will pass on the noise only if the arrival timing window of the noise overlaps with the clock s setup and hold window. 6. Non-linear superposition of Noise sources This paper [5] proposes a new model for accurate Worst Case Noise estimation. The key contribution of this paper is the model for drivers of victim nets in the presence of large noises. The problem with large noises being that the transistors connected to the output victim node will be driven into saturation region and hence the Worst case noise is no longer the superposition of noises contributed from input noise propagation and output capacitive coupling noise. The below table illustrates the fact that the propagated noise and injected noise cannot be simply summed up to get the worst case noise, as its value compared to that of spice simulation shows significant overestimation. The key idea behind more accurate noise estimation comes from the fact that this paper models the victim driver using current source which is dependent on the output node voltage. And the aggressor is modeled as thevenin voltage source as usual since it was found that this doesn t affect accuracy. So the circuit model for noise calculation is as shown in Figure 17.
Now the accurate total noise glitch at the Victim driver point, due to input propagated noise is found using Quasi Linear Transient Analysis is given by a Two pole model: Waveform-collapsing algorithm expresses the analytical triplet in terms of noise glitch parameters like Amplitude VM, Area A, width and time-to-peak, with the initial relation as shown in the below equation. Now V(t) is obtained by computing the roots of the following equation. The noise at the output due to multiple aggressors can be found out using Model Order reduction which reduces the network to R and C segments. Finally, the total noise contributed by both input propagated noise and aggressor induced noise is given by the below equation The first part of the above equation is solved in reality using Model Order Reduction technique and the second part using the two port model of Quasi Trans linear Analysis. The results show that the accuracy has good improvements for this method compared to the traditional super position principle applied in all the previous works.
7. Conclusions This report starts by defining Static Noise Margin and the importance of Static Noise Analysis in the first and second chapters. The noise margin criterion that Is described in [1] is presented and the analysis in [2] is described. The seed paper HARMONY [2] is discussed in detail where the two-level hierarchical flow involving MACRO and GLOBAL levels performs full-chip static noise estimation. At MACRO level, the noise graph representation and sensitization formulation are described in detail with examples to show how to arrive at the worst case noise at a node due to various sources. The GLOBAL level method that performs noise estimation on top of details from macro step is presented. The method is conclusively a base for general static noise analysis estimation. The next paper [3] describes aggressor alignment technique that shows major improvements over the methods used in Harmony all of which contribute to more accurate estimation. The basic idea that worst case noise is not generated due to aggressors aligned in time is described along with the more accurate method to find out the true worst case noise, along with the aggressor arrival time constraints. The next paper [4] which contributes new methods to accurately predict static noise injection using noise window propagation and register sensitive window computation was presented. This has added advantage to that of [3] because of noise window propagation. Standard cell non-linear effects on noise glitch waveform that is described in [5]. This shows that existing papers [1] to [4] consider the linear superposition of noise which is inaccurate and improves on it. In summary, the seed paper for Static Noise Analysis is analyzed and presented in detailed followed by study of papers, in chronological order, that show good improvements over the seed paper. The key contributions of each of the papers are described at the beginning of their corresponding sections. The new methods that these papers propose have been described along with results. 8. References [1] Jan Lohstroh Evert Seevinck, Andjan De Groot Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence [2] K. L. Shepard, V. Narayanan, P. C. Elmendorf, and G. Zheng, Global Harmony: Coupled Noise Analysis for Full- Chip RC Interconnect Networks, in Proc. Intl. Conf. on Computer- Aided Design, Nov. 1997, pp.139-146. [3] L. H. Chen, M. Marek-Sadowska, Aggressor alignment for worst-case crosstalk noise, IEEE Tran. Computer-Aided Design, vol. 20, no. 5, pp. 612-621. May 2001. [4] Ken Tseng, Vinod Kariat Static Noise Analysis with Noise Windows, Annual ACM IEEE Design Automation Conference, 2003. [5] Cristiano Forzan, Davide Pandini A Complete Methodology for an Accurate Static Noise Analysis Proceedings of the conference on Design, automation and test in Europe, p.812, March 04-08, 2005