Interntionl Journl of Computer Theory nd Engineering, Vol. 8, No. 3, June 206 Logic Design of Elementry unctionl Opertors in Quternry Alger Asif iyz, Srh Nhr Chowdhury, nd Khndkr Mohmmd Ishtik Astrct Multivlued logic is n extension of Boolen lger with high rdix pproches nd is preferle over conventionl inry logic opertions for reduction in interconnection cost, chip re oth on-chip nd etween chips nd high informtion hnding cpility. This pper includes the design of elementry comintionl quternry opertors tht hve sufficient representtive cpility to efficiently implement in intricte quternry rithmetic circuits. Design of severl comintionl logic circuits hve een presented which cn function individully nd in logic locks for designing further complex circuits resulting in reduction of circuit complexity nd etter speed processing in integrted circuit technology. Index Terms Cycle gte, mx nd min gte, multivlued logic, quternry lger. I. INTRODUCTION Binry logic hs een predominnt in emedded system nd fundmentl for computer progrmming nd mthemticl logic due to its esy ccessiility nd widespred use in logic circuits. Operting with inry logic implies to controlling the rel world with computers nd tht n lterntive improved pproch with etter usge of trnsmission pth, storge nd processing of lrge mount of informtion in digitl signl processing even exist seems somewht impossile. Yet, Moore s lw sttes tht, the numer of trnsistors on integrted circuits doules pproximtely every two yers. As this lw hs een y fr proven ccurte, it is high time we considered lterntive pproches to reduce this tremendous positive rte of elements used in integrted circuits. It hs een suggested tht y incresing the processing speed, memory cpcity, sensors or memory sttes, this significnt rte cn e inhiited to n exponentil rte. But, due to the inherent limittion dt representtion system of only two distinct levels {0, }, inry logic impedes the scope for multiple sttes nd lcks high speed nd informtion hndling cpcity. On the other hnd, multivlued numer systems, such s ternry nd quternry systems with rdix more thn 2 (p>2) emerges with the immedite enefit of lrger informtion hndling nd storge cpcities. Multivlued logic system introduces new opertors in ddition to inry vlues {0, } nd is proposed extension of the ide tht n vlued logic cn e used insted of two logicl vlues (tht is, true or flse, logic high or low) where n>2 []. Perhps one of the most tngile immedite enefits of Mnuscript received Septemer 9, 204 revised Jnury 5, 205. The uthors were with the Ahsnullh University of Science nd Technology, Dhk, Bngldesh (e-mil: sif.fiyz@gmil.com). higher-rdix pproches like quternry logic lies in their potentil for reduction of the wiring congestion nd interconnection cost [2]. Using single conductor to trnsmit three or more discrete voltge or current vlues llows for greter informtion content per wire nd thus results in circuit with reduced conductors nd logic gtes thn the inry-vlued counterprt. urthermore modeling of mny complex logic systems nd ssocited lgers re possile due to the exponentilly incresing numer of opertors with respect to the crdinlity of the multiple logic vlues. Although multivlued logic prticulrly quternry lger is not s widespred s inry, it hs gined much pprecition in recent yers due to its higher informtion hndling cpcity of much more complex lgorithms in emerging topics like opticl nd quntum computing []. Tht is why it is prerequisite to express its fundmentl opertors in terms of equtions nd logic digrm for further implementtion in multiplex lgorithms. In this pper, we hve designed some importnt functions like mx, min, mod-sum, mod-difference, successor, predecessor, 2 nd level successor or predecessor nd 3 rd level successor nd predecessor using erlier proposed logic functions nd sic opertors proposed in [3]-[6] which cn e implemented susequently in composite circuits. II. QUATERNARY ALGEBRA Multivlued logic (MVL) or noninry-vlued system utilizes vriles tht cn tke on discrete set of vlues with crdinlity of n 3 nd quternry lger which hs een derived s propositionl or quntum logic from MVL lger is defined over four finite sets of logic vlues []. Hence, while multi vlued logic dels with infinite numer of vlues s discrete vriles, quternry lger is sed upon the discrete vriles {0,, 2, 3} including the inry vlues {0, }. Quternry sttes {0,, 2, 3} with set of opertors nd xioms re used to define quternry lger. Ech of the quternry sttes {0,, 2, 3} hs its two its inry equivlents 00 (solute low), 0 (intermedite low), 0 (intermedite high) nd (solute high) nd ech of the quternry its is clled qudit [3], [7], when expressed in numers. The logic vlues cn lso e indicted y two inry digits nd 0, respectively which is inscried nd pcked together using the following notion A={, 0} where the term 2 + 0 denotes the mgnitude of the vrile A in deciml system [4]. Quternry sttes re su ctegorized into symmetricl nd symmetricl sed upon their position of its. If the its of the inry equivlent of quternry sttes interchnge their position nd still the quternry sttes remin unchnged then they re known s symmetricl. DOI: 0.7763/IJCTE.206.V8.053 250
Interntionl Journl of Computer Theory nd Engineering, Vol. 8, No. 3, June 206 Asolute sttes (0, 3) re symmetricl s the chnge of its in inry equivlent does not chnge the corresponding quternry vlue. If the trnsposition of position of its chnges the corresponding inry vlue then they re known s symmetricl. Intermedite sttes (, 2) re symmetricl s interchnging the inry equivlents chnges the quternry stte to 2 nd vice vers [6]. Quternry lger is in congruence with inry logic in terms of the sic opertors like OR, AND, BUER, BASIC INVERTER, XOR, BASIC NAND, BASIC NOR nd BASIC XNOR nd tht is why the interfcing of inry to quternry cn esily e conducted y just using n encoder. So, quternry lger cn e used s models for the initil design of logic circuits whether they re implemented with MVL signl levels or inry fter eing encoded. Agin, using the minstrem fundmentl opertors, the functionl opertors which re nlogous to inry logic cn esily e derived nd ll the logic locks of quternry re comptile with inry logic design mking it prgon for dul purpose. x y x=y? x y x=y? min min ig.. Design of Min gte using sic gtes. III. PROPOSED IDEA Just like Boolen lger, it is necessry to provide n effective logic design nd well-defined frmework for expressing nd mnipulting functions in quternry lger. Comintionl circuit is vitl element for ny digitl system. In mny pplictions, tht is why, it is impertive tht the opertors of the lger hve simple nd efficient circuit implementtions for reducing circuit complexity. Although functions like mx, min, cycle gte (forwrd nd reverse cycle), successor nd predecessor, 2 nd level successor nd predecessor hve lredy een introduced [3], [4], yet, no specifictions to the truth tle, logic digrm nd corresponding equtions hve een stted so fr ting the process of further implementtion of these functions in complex circuitry. The pper proposes the techniques for finding the truth tle, logic digrm nd the eqution for some consequentil functionl opertors like mx, min, cycle gte (forwrd nd reverse cycle), successor nd predecessor, 2 nd level successor nd predecessor which cn e further implemented to solve circuit complexity. Henceforth, our proposed quternry logic designs cn e integrted efficiently for designing some conventionl circuits. A. Min nd Mx Gte Seeing in ig. nd ig. 2. The Min function is used to compre the minimum mong the severl literls [3]. A representtion of quternry switching function tht is nlogous (ut not identicl) to the inry sum of minterms representtion cn e formulted using the Mx function in plce of the inry inclusive OR function nd product terms my e formed using the Min function in plce of the inry AND opertion. But fter otining the truth tle of Min nd compring it with the corresponding truth tle for AND function, it cn e concluded tht the Min function is similr to AND function with the exception for the prticulr cse of inputs nd 2 or 2 nd [4] (see Tle I). Similrly, min min ig. 2. Design of Mx gte using sic gtes. the comprison etween Mx nd OR opertors lso shows resemlnce in their properties nd output except when the inputs re nd 2 or 2 nd [4]. Mny of the existing quternry logic schemes hve min nd mx s opertors nd these opertors hve lredy een relized physiclly [8]. But the lck of representtion in logic design mkes it difficult to implement these functions in complex circuits. So, we hve proposed new set of equtions congruous with the estlished truth tle long with their respective complementry logic design which re of their simplest form nd re further verified using mtl. Min gte function cn e represented y the following eqution. Min (A, B) = A.B when or otherwise A nd B 2 A 2 nd B Clerly we cn understnd tht while designing the logic digrm we cnnot replce min function with AND gte rther we hve to undergo dditionl chnges to otin the output for (, 2) nd (2, ). or designing the logic digrm therefore we hve utilized the concepts of specil gtes, different theorems nd properties of quternry lger. Initilly in order to just otin (, 2) nd (2, ) we hve utilized the concept of itswp nd equity functions. We know, itswp opertor interchnges the symmetric inputs keeping the symmetric unchnged nd equity function provides the output 3 for the similr inputs nd rest 0 [4]. So together we otin 3 for (0, 0), (, 2), (2, ) (3, 3) nd 0 otherwise. In the very next step, we need to design function which seprtes the inputs (0, 0) nd (3, 3) from the other two sets. Oserving the pttern, we hve introduced XOR opertor here which provides 0 for similr inputs nd greter thn for dissimilrity. Although fter using this function, we hve seprted the desired functions yet we lose the output 3 for inputs (, 2) nd (2, ). So, in order to otin this output we hve utilized one of the 25
Interntionl Journl of Computer Theory nd Engineering, Vol. 8, No. 3, June 206 properties of quternry lger which is B. orwrd Cycle nd Reverse Cycle Gte 3 0 0 0 We hve focused on the two outputs 3 nd 0 for utilizing the property.3 = nd.0 = 0 of AND gte. As result, we hve plced n AND gte t the next step in order to otin n output 3 for only inputs (, 2) nd (2, ) nd 0 otherwise. We then plce n inverter connected to n AND gte to ensure n output of 3 for ny comintion of input prt from (, 2) nd (2, ) for which it is 0. After this very step we need to convert the output 0 for inputs (, 2) nd (2, ) to keeping the rest unchnged y utilizing the property, ig. 3. Design of orwrd cycle gte using sic gtes. 0. 0 3 Plcing it efore the inverter we otin the desired result which is then connected to n OR gte to provide the required output. The logic design of min function cn e mnipulted into different wys through different comintions of gtes, yet we mnged to ensure novel design with minimum gtes fter going through different comintions. We cn lso oserve the equtions of Mx gte derived from perceiving the similrity of this function with other sic functions nd the truth tle. 2 when A nd B 2 Mx (A, B) = or A 2 nd B A B otherwise In cse of mx function similrly, while compring with OR function we oserve similrity except for (, 2) nd (2, ). As result we use the sme procedure stted ove to seprte the contrdictory functions from the rest nd then using the properties of quternry lger to otin the required result. TABLE I: TRUTH TABLE OR MAX UNCTION, MIN UNCTION, AND UNCTION AND OR UNCTION B A AND MIN OR MAX 0 0 0 0 0 0 0 0 0 0 2 0 0 2 2 0 3 0 0 3 3 0 0 0 2 0 3 2 3 3 3 2 0 0 0 2 2 2 0 3 2 2 2 2 2 2 2 2 3 2 2 3 3 3 0 0 0 3 3 3 3 3 3 2 2 2 3 3 3 3 3 3 3 3 ig. 4. Design of Reverse cycle gte using sic gtes. TABLE II: TRUTH TABLE OR ORWARD CYCLE UNCTION, REVERSE CYCLE UNCTION AND XOR UNCTION B A XOR orwrd Cycle Reverse Cycle 0 0 0 0 0 0 0 2 2 2 2 0 3 3 3 3 0 3 0 2 0 2 3 3 3 2 0 2 2 0 2 2 2 2 3 3 3 2 2 0 0 0 2 3 3 0 3 3 3 2 0 2 3 2 3 3 3 0 2 0 Seeing in ig. 3 nd ig. 4, orwrd cycle or mod-sum nd reverse cycle or mod-difference re cycle gtes where the output vries tking the reference point s one input nd vrying with respect to the quternry vlue of the other input [3]. In cse of forwrd cycle gte, with respect to one reference point the movement of the input quternry vlue is clockwise nd in cse of reverse gte it is nticlockwise. or exmple, for the two input vlues s nd 3, if the reference vlue is, then the output fter moving in clockwise direction y shifting twice ecomes 0. On the contrry, for the reverse cycle gte the output fter moving in n nticlockwise direction ecomes 2. The following eqution is derived nd the logic digrm is further designed y oserving the truth 252
Interntionl Journl of Computer Theory nd Engineering, Vol. 8, No. 3, June 206 tle constructed y clculting the logicl output nd then verified using mtl. orwrd cycle (A, B) = 0 when A nd B 3 or A 3 nd B 2 when A B or A B 3 A B otherwise Oserving the truth tle of forwrd cycle (see Tle II), we conclude the similrity etween forwrd cycle nd XOR gte except for inputs (, ), (, 3), (3, ) nd (3, 3). As result while designing the logic digrm prt from plcing XOR gte we need to redesign our circuit in order to otin the required output for the exceptions. Oserving the output we cn speculte tht the ntonymous output vries from 0 to 2 nd vice vers. Utilizing this understnding we hve plced two BITSWAP gtes in order to chnge the exceptionl symmetric input to 2 nd further plcing n AND gte which provides n output (>=2) for the exceptionl inputs nd output (<=) otherwise. After tht, using n INVERTER nd the following function, ' ˆ 0 2 2 We otin n output of 2 for the exceptionl inputs nd 0 otherwise. Then using just n XOR gte with this prticulr comintion we ttin the desired output. Similrly, the Reverse cycle gte eqution eing derived is: Reverse cycle (A, B) = when A 2 nd B or A 0 nd B 3 3 when A 0 nd B or A 2 nd B 3 A B otherwise Oserving the truth tle of the Reverse cycle gte nd compring the output with tht of XOR, we hve used different comintions nd properties to otin the corresponding logic digrm. C. Successor nd Predecessor Gte 2 3 ig. 5. Design of Successor gte using sic gtes. 3 ig. 6. Design of Predecessor gte using sic gtes. Seeing in ig. 5 nd ig. 6, While functions like forwrd nd reverse cycle shows us the interdependence of the quternry inputs, functions like successor nd predecessor give us the desire output s per the numer of times the input shifts eing fixed eforehnd [3]. Predecessor or 3 rd level successor gtes give the preceding vlue or the output fter the input shifts three times in the clockwise direction for the prticulr vlue of input. or exmple, for prticulr input of, we cn otin the precedent vlue 0 or y shifting the input three times in the clockwise direction. Similrly, using the successor or 3 rd level predecessor gte, we cn otin the succeeding vlue which is 2 for the prticulr ove mentioned cse. The logic digrms re designed gin y compring the output with different properties of quternry opertors nd pplying different comintions of gtes. Successor gte (A) = (( A.) ( A 2) Predecessor gte (A) = (( A.) A TABLE III: TRUTH TABLE OR SUCCESSOR UNCTION, PREDECESSOR UNCTION, 2ND LEVEL SUCCESSOR OR 2ND LEVEL PREDECESSOR UNCTION, 3RD LEVEL SUCCESSOR UNCTION AND 3RD LEVEL PREDECESSOR UNCTION A Successor Predecessor 2nd level successor or 2nd level predecessor 3rd level successor 3rd level predecessor 0 3 2 3 2 0 3 0 2 2 3 0 3 3 0 2 2 0 D. 2 nd Level Successor or 2 nd Level Predecessor Gte Seeing ig. 7, Just like Successor or Predecessor gte, using 2 nd level successor or 2 nd level predecessor gte, we cn otin the corresponding 2 nd preceding nd succeeding vlues fter the input eing shifted twice. We cn conclude tht using different levels of successor nd predecessor gtes we cn otin ny desired vlue t ny position which cn e of immense enefit while designing complex logic circuits. The eqution for this prticulr cse hs een derived s follows: 2 nd level successor gte = 2 nd level predecessor gte = ( A 2) 253
Interntionl Journl of Computer Theory nd Engineering, Vol. 8, No. 3, June 206 2 quntum technology contriuting to the design of novel electron devices like Cron Nnotue Trnsistor, inet, G4-ET, Silicon Nnowire ET, etc. where quternry logic is preferle rther thn inry for fst processing. 2 2 ig. 7. Design of 2nd Level Successor or 2nd Level Predecessor gte using sic gtes. IV. UTURE WORKS Although the corresponding eqution nd logic digrm derived for the functionl opertors cn e esily interfced nd hs een minimized using different comintions, further work hs to e done to mke it more comptile y deriving different theorems nd properties s the centrl concept of functionl completeness of quternry lger is still the underlying concept to e considered. The comintionl circuits designed in this pper cn e effectuted for designing further complex circuits like dder, multiplier, sutrctor, multiplexer, comprtor, flip-flops nd other elementry sequentil circuits. Mny of the more recently pproved lgers hve een developed for the purpose of modeling MVL circuits sed upon prticulr electronic components to e used s primitive circuit elements in their construction nd the logic design of elementry functionl opertors rings us one step closer to physicl implementtion of quternry circuits in the high performnce microprocessor. V. CONCLUSION In this pper, we hve constructed the logic design nd respective equtions of foundtionl functionl opertors nd tested ech derived eqution using mtl. Despite the inconsistency of output of the fundmentl opertors in quternry lger, we hve mnged to formulte novel designs for relevnt functions like mx nd min functions which re considered the frmework of quternry lger ecuse of their implementtion s set of mx, min nd equlity opertors which is sufficient enough to express ny quternry function lgericlly. We hve lso depicted opertors like predecessor nd successor through their logic digrm which hve historiclly een considered s distinct since they hve direct circuit implementtions nd re prticulr cses of generl cycle opertion. Therefore, for the significnt efficcy of these opertors, new lgeric nd logic design techniques hve een developed in this pper which cn e utilized in some future novel technology or implementtion. Although inry logic cn e professed s the pivot of controlling the emedded fundmentl nd digitl system of modern times, yet quternry lger imposes some fetures which cn provide immense enefit to the VLSI nd REERENCES [] S Hurst, Multiple-vlued logic Its sttus nd its future, IEEE Trnsctions on Computers, vol. C-33, no. 2, pp. 60-79, 984. [2] A. M. H. Khn, Reversile reliztion of quternry decoder, multiplexer, nd demultiplexer circuits, Engineering Letters, vol. 5, no. 2, pp. 203-207, 2007. [3] D. M. Miller nd M. A. Thorton, Multiple vlued logic: Concepts nd representtions, Synthesis Lectures on Digitl Circuits nd Systems, Morgn & Clypool Pulishers, 2007. [4] I. Jhngir, A. Ds, nd M. Hsn, ormultion nd development of novel quternry Alger, rxiv Preprint rxiv: 08.5497, 20. [5] A. Ds, I. Jhngir, M. Hsn, nd S. Hossin, On the design nd nlysis of quternry seril nd prllel dders, in Proc. IEEE Region 0 Conference, 200, p. 69. [6] I. Jhngir, N. M. D. Hsn, S. Islm, N. A. Siddique, nd M. M. Hsn, Development of novel quternry lger with the design of some useful logic locks, in Proc. 2 th Interntionl Conference on Computers nd Informtion Technology, 2009, p. 07. [7] Y. A. Gidhni nd N. K. Monic, Design of some useful logic locks using quternry Alger, in Proc. CEE 20, Indi, 20. [8] V. Ptel nd K. S. Gurumurthy, Design of high performnce quternry dders, Interntionl Journl of Computer Theory nd Engineering, vol. 2, no. 6, Decemer 200. (IEEE). (IEEE) since 202. Asif iyz is currently pursuing his chelor degree in electricl nd electronic engineering from Ahsnullh University of Science nd Technology, Dhk, Bngldesh. His reserch interests include signl processing, pttern recognition, nnotechnology, quternry logic, microwve communiction etc. He is currently student memer of the Institute of Electricl nd Electronics Engineers Srh Nhr Chowdhury is n undergrdute student in electricl nd electronic engineering of Ahsnullh University of Science nd Technology, Bngldesh. She is currently working s the secretry of Engineering Students Assocition of Bngldesh (ESAB). Her reserch interests include solr cells, renewle energy, orgnic trnsistors, nnotechnology nd quternry lger. She is student memer of the Institute of Electricl nd Electronics Engineers Khndkr Mohmmd Ishtik ws orn in Bngldesh in 986. He grduted from the Electricl nd Electronic Engineering Deprtment of Ahsnullh University of Science nd Technology (AUST). Currently he is working s n ssistnt professor of the EEE Deprtment in AUST. He is memer of the Institute of Electricl nd Electronics Engineers (IEEE). His reserch interests include nnotechnology, solr cells, quternry lger, signl processing nd nlysis. 254