AN ERROR LIMITED AREA EFFICIENT TRUNCATED MULTIPLIER FOR IMAGE COMPRESSION

AN ERROR LIMITED AREA EFFICIENT TRUNCATED MULTIPLIER FOR IMAGE COMPRESSION K.Mahesh #1, M.Pushpalatha *2 #1 M.Phil.,(Scholar), Padmavani Arts and Science College. *2 Assistant Professor, Padmavani Arts and Science College. Abstract - DSP and multimedia applications have fixed width property which has equal number of input and output bit width, so these applications require fixed width multiplier. But fixed width multiplier or multiplier often leads to error at the resulting output. The need is to design multiplier of required precision that can be applied to different field of work with optimization such as area, accuracy or power. A fixed precision multiplier with truncation error limited by 1 ulp (unit of least position) is designed and implemented in Image Compression using Discrete Wavelet Transform (DWT).The multiplier design involves truncating the least significant bit (LSB) part of the multiplication result by operations such as deletion, reduction, truncation, rounding and addition of final partial products. The Image compression technique is based on real time signal processing. Image Compression using DWT with this area efficient multiplier results in better Image quality, having high PSNR (Peak Signal to Noise ratio) value, low energy and area consumption. Index Terms - Truncation, fixed width multiplier, optimization, reduction, Image Compression I. INTRODUCTION is the most essential functional block in any digital signal processing architecture. For DSP applications requiring large bit width size, fixed width multipliers were designed involving low area cost. The fixed width multiplier produces n bits at the output instead of 2n as that of a full precision multiplier for a n x n multiplier. The fixed width multiplier is a subset of multiplier. Fixed width multipliers are used in applications such as convolution, function approximation, filtering, fast Fourier or discrete cosine transform. The multiplier gives truncation error when the 2n product bits are to required precision. This truncation error is usually not desirable and produces undesired results for any application. Previous techniques have used addition compensated circuits to overcome this error but this instead increases the complexity of the design[3].some multiplier design methodology were introduced depending upon how the errors were created due to the deletion of the LSB (least significant bits) partial product bits namely constant and variable correction. 82 Image compression is the method of removing the redundant information from the image so that only essential and required information can be stored to reduce the storage space, transmission bandwidth and transmission time. The essential information is extracted by various transform techniques such that it can be reconstructed without losing quality and information of the image. The main purpose of image compression is to reduce the redundancy and irrelevancy present in the image, so that it can be stored and transmitted efficiently. The compressed image is represented by less number of bits, as compared to the original image. Thus, the required storage size will be reduced, consequently maximum images can be stored and it can transferred in faster way to save the time, transmission bandwidth. In image compression technique, spectral and spatial redundancy should be reduced as much as possible. There are many applications where the image compression is used such as Health Industries, Retail Stores, Security industries etc. There are various algorithms used for image compression such as DFT, DCT and DWT. Images compressed and reconstructed using multipliers are shown to be almost identical to images processed using standard multipliers, but with least significant bits of the multiplication matrix eliminated, there is a significant reduction in partial product bits resulting in reduced multiplier size and power consumption. Hence there is a significant overall power saving for the DSP system. II. BACKGROUND Application specific processors have developed the need for high performance, maximum speed multipliers. As a result Wallace proposed a fast multiplier, followed by Dadda and then Braun s Carry Save scheme. Wallace and Dadda scheme offers fast multiplication but need complexity and cost attention. The multiplication of an M bit multiplicand by a N bit multiplier yield an N by M matrix of partial products. Many parallel multiplication algorithm has been given to reduce chip size and increase the speed of the multiplier. Now the need is to design multiplier of required precision that can be applied to DSP and multimedia applications such as Image Compression with required optimization such as area, accuracy or power. The challenge lies in the fact that the optimization is achieved with minimum amount of impact on other parameters and with the design of the multiplier for a specific application. Also there is a requirement for Image compression technique which provides

high compression with quality reconstruction. For this purpose many compression techniques i.e. scalar/vector quantization, differential encoding, predictive image coding, transform coding have been introduced based on different performance measure such as Peak Signal to Noise Ratio (PSNR), Mean Square Error (MSE) etc. Among all these, transform coding is most efficient especially at low bit rate. Transform coding relies on the principle that pixels in an image show a certain level of correlation with their neighbouring pixels. Depending on the compression techniques the image can be reconstructed with and without perceptual loss. In lossless compression, the reconstructed image after compression is numerically identical to the original image. In lossy compression scheme, the reconstructed image contains degradation relative to the original. Transform coding, which applies a Fourier-related transform such as DCT and Wavelet Transform such as DWT are the most commonly used approach. The compression standard (JPEG2000) in recent times is based on DWT and provides better quality of decoded images. This paper shows efficient performance of real time Image Compression technique using DWT with the implementation of error limited multiplier in terms of hardware complexity and quality of the image reconstruction. III. METHODOLOGY A.Constant Correction Generally the truncation error may be classified as reduction error and rounding error. The reduction error occurs when least significant columns of the multiplication matrix are not considered to compute the product and rounding error arises when the product is rounded to required n bits. To overcome these two sources of errors a constant termed as correction constant is added to the most significant columns of the multiplication matrix[2].most of the correction constants are used as zero, thus don t require any additional hardware compensational components or circuits. A standard parallel multiplier may yield 2n bits at the result for a n x n applied input bits as shown in Fig 1. Fig 2 shows a multiplier with correction constants c0, c1 added to the multiplication matrix. The idea of correction constant is to ensure that the error due to truncation is eliminated or minimized with the constant added to a particular column. Fig 1.Multiplication Matrix. Fig 2. Truncated Multiplication Matrix The value of the correction constant is chosen such that it can be added to the partial products with few resources required. B. Image Compression using DWT Image compression is one of the important applications of wavelet. Wavelets are mathematical functions that can be used to transform one functional representation to another. Wavelet transform performs analysis of multi resolution image. Multi resolution is simultaneous representation of image on different resolution levels. Wavelet transform represents an image as sum of the wavelet function with different location and scale. The decomposition of an image into wavelets involves two pair of transforms, one for high frequencies related to the detailed portion of the image and other for low frequencies related to the smooth part of the images. Images are considered as two dimensional signals, they change both horizontally and vertically, thus 2-Dimensional wavelet analysis must be used for images. Wavelet compression technique uses the wavelet filters for image decomposition into divided approximation and detailed sub division. IV. TRUNCATED MULTIPLIER A tree multiplier involves steps such as generation of partial products, reduction of partial products and the final addition to sum up the final two rows of partial product matrix. The two famous tree reduction methodologies are Wallace and Dadda tree. Wallace tree [4] combines the partial products as fast as possible thus using more hardware resources at the adder levels while Dadda multiplier [5] considers the critical path (column height) first, thus combines the partial products as late as possible thus using least number of resources at the adder level but wider bit size for the CPA (carry propagate adder).a reduced area reduction method was given previously to minimize the bit width of CPA. In the current method two schemes for tree reduction is presented i.e. Scheme 1 and Scheme 2 as shown in Fig 3.The multiplier discussed in the paper uses both the schemes presented. Scheme 1 aims at reducing the number of HA at the reduction level because as compared to half adder, compression ratio of full adder exhibits better reduction efficiency. Scheme 1 doesn t necessary mean that the number of bits after reduction is one. Scheme 2 is similar to Dadda multiplier. 83

Fig 3.Tree Reduction of 8 x8 multiplier based on scheme 1 and scheme 2 V. TRUNCATED MULTIPLIER DESIGN The design method consists of various stages such as deletion, reduction, truncation and rounding. Consider an 8 x 8 multiplier with M=N=8, where M is multiplicand and N is the multiplier. If final product bits required is P=8, so the number of bits is given by T=M+N-P. Let s discuss each of the stages in detail. A. Deletion This steps removes or deletes the least significant partial product bits as long as the deletion error is bounded by -1/2 ulp E D 0 or error is not more than 2 -P-1 with first two rows remains unchanged and bits to be deleted are selected from column 1 to column T-1.The constant added is 1 D, which limits the error to be bounded by -1/4 ulp E D 1/4 ulp. B. Reduction Scheme 2 reduction method is used from column 1 to column T-1 since we will truncate the lsb bits of the product at the final stage we can use this scheme which requires no optimized carry propagate adder (CPA). From column T to column M+N scheme 1 reduction is used to determine whether an half adder is required or not and it can minimize the carry propagate adder(cpa) bit size. C. Truncation After reduction the next step is truncation from first row of n-1 bits from column 1 to column n-1.truncation error is limited by -1/2 ulp E T 0.A constant of 1/4 ulp reduces the error to 1/4 ulp E T 0. D.Rounding and Final Addition Partial Products bits from column 2 to column n-1 are eliminated before the final addition because these bits are the only bits left in the column after deletion and truncation processes, thus do not affect the carry bit to column n+1 during the rounding process and are not considered. We add a constant 84 of 1/2 ulp before the final CPA for achieve rounding error bounded by -1/2 ulp E R 1/2 ulp. The total error during all the stages can be summed up to be limited as -ulp < E= (E D +E T +E R ) ulp. All the three bias constant can be added together to be added at column n+1 without increasing the height of the matrix of partial products. We also use the the simplified version of half adder and full adder cells which are nothing but the half adder and full adder without output sum bits and only carry being generated,thus reducing the adder computation. We implement scheme 1 for higher order bits which does not cause the column height to reduce to 1 resulting in carry ripple. The error limit for deletion,truncation and rounding stages are given as -2 -P-1 E D 0 (1) -2 -P-1 E T 0 (2) -2 -P-1 E R 2 -P-1 (3) VI. REAL TIME IMAGE COMPRESSION Wavelet compression is the technique considered for image compression which aims to store the information in the image in little space possible such as a file. Wavelet compression transient data can be represented by small amount of data. In DWT the filter frequency response is in the form of floating point (filter coefficients).in filter design the corresponding coefficients will be pre-processed to be used as an integer after floating point to binary conversion. The input image as text file is in the analog form is converted to integer value to be processed with digital filter along with the filter coefficients. The output will be an Image in the form of integer which is post processed to get back the original reconstructed image. The quality of image reconstructed back is based on PSNR (Peak Signal to noise ratio), commonly used to measure the quality of reconstruction for image compression. The signal here is the original image, and the noise is the error introduced by compression. A higher PSNR generally indicates that the reconstruction is of higher quality. Typical values for the PSNR in image and video compression are between 30 and 50 db, provided the bit depth is 8 bit, where higher is better. For 16 bit data typical values for the PSNR are between 60 and 80 db. Wavelet Transform provides frequency of the signal along with the time associated with those frequencies. Wavelets are useful for compressing signals. They can be used to process and improve signals, mainly in fields such as medical imaging where image degradation is not tolerated. Wavelets are used to remove noise in an image. The analysis of 2D wavelet uses the same mother wavelets but requires an extra step at every level of decomposition. In 2D, the images are considered as matrices with N rows and M columns. The decomposition of an image into wavelets involves a pair of waveforms, one to represent the high frequency corresponding to the detailed part of the image (wavelet function) and the other for low frequency or smooth parts of an image (scaling function). At

every level of decomposition the horizontal data is filtered, the approximation and details produced from this are filtered on columns. At each level, four sub-images are obtained; the approximation along with the vertical detail, the horizontal detail and finally the diagonal detail. Wavelet function for 2-D DWT can be obtained by multiplying wavelet functions (ψ(x,y)) and scaling function (φ(x,y)). After first level decomposition we get four details of image those are, column. Output of the above step is supposed to be L2 and H2 and they are combined to get A2, where A2=. Now, A2 is down sampled by 2 to get compressed image. We get the compressed image by using one level of decomposition, to provide high compression ratio we need to follow above steps more number of times depending on number of decomposition level required. Approximate details ψ(x,y)= φ(x ) φ(y ) Horizontal details ψ(x,y)= φ(x ) Ψ (y ) Vertical details ψ(x,y)= ψ(x )φ(y ) After applying the 2-D filter bank at a given level n, the detail coefficients are output, while the whole filter bank is applied again upon the approximation image until the maximum resolution is achieved. Fig.4 shows wavelet filter decomposition. The sub-bands are labelled by using the following notations [8], 1) LLn represents the approximation image n th level of decomposition, resulting from low-pass filtering in the vertical and horizontal both the directions. 2) LHn represents the horizontal details at n th level of decomposition and obtained from horizontal low-pass filtering and vertical high-pass filtering. 3) HLn represents the extracted vertical details, at n th level of decomposition and obtained from vertical low-pass filtering and horizontal high-pass filtering. 4) HHn represents the diagonal details at n th level of decomposition and obtained from high-pass filtering in both the directions. The LPF and HPF images are extracted from compressed image by simply taking upper half rectangle of matrix (LPF image) and down half rectangle (HPF image). Then both images are up sampled by 2. The summation of both images into one single image is called B1. Again LPF image and HPF image are extracted by dividing vertically. Two halves obtained are filtered through LPF and HPF, summation of these halves gives the reconstructed image. VII. EXPERIMENTAL RESULTS The Simulation is carried out with ModelSim Software tool and the synthesis of the design is carried out by using Quartus II along with the implementation of the design in Altera Cyclone II FPGA. The preprocessing and post processing of real time signals is carried out using MATLAB. A comparative analysis of various n x n bit standard and multiplier in terms of power and area is shown in table 1. TABLE 1 COMPARITIVE ANALYSIS BETWEEN MULTIPLIERS Total logic elements Total registers Dissipated Power(mW) Standard multiplier Tree Based Error Efficient Truncated 298 207 80.86 223 112 78.96 210 108 78.02 Fig 4.Wavelet Filter Decomposition Original image is passed through HPF (High pass Filter) and LPF (Low pass Filter) by applying filter first on each row. Output of the both image resulting from LPF and HPF is considered as L1 and H1 and they are combined into A1, where A1= [L1, H1]. After that A1 is down sampled by 2. Again A1 is passed through HPF and LPF by applying filter now on each 85 DWT comprises between compression ratio and quality of reconstructed image, it adds speckle noise to the image for improvement in the reconstructed image. Hence DWT technique is useful in medical applications. DWT gives a better image quality with better PSNR value when implemented with error efficient multiplier. Fig 5 shows the original image to be compressed. Fig 6 corresponds to the image compressed using

standard multiplier. Fig 7 corresponds to the compressed image using the error efficient multiplier. 10 40.02 40.54 40 33.26 33.98 80 29.42 30.73 90 28.20 29.81 VIII. CONCLUSION Fig 5.Original Image Fig 6.Compressed Image using standard Truncated Fig 7.Compressed image using the error efficient multiplier A comparative analysis of PSNR value for reconstructed image using MATLAB Simulation of JPEG image for different threshold values is shown in table 2. TABLE 2 An error limited area efficient multiplier was designed and implemented in image compression using Wavelet Transform.Experimental results were studied, including power measurements and functional verification of multiplier. Optimization in terms of area and PSNR value for efficient implementation of image compression technique with different threshold levels were presented. The system was successfully implemented using CYCLONE II FPGA kit. The cost of such a design is marginally reduced due to low area requirement. It is also demonstrated that the design can be easily reconfigured to match a wide range of performance requirements and cost constraints. The future work can be extended to implementation of Image compression technique using Hybrid (DCT-DWT) transform with the error efficient multiplier. REFERENCES [1] Hou-Jen Ko and Shen-Fu Hsiao Design and application of Faithfully Rounded and Truncated with combined deletion reduction truncation and rounding ; IEEE transactions on Circuits and Systems-II: Express Briefs, Vol.58.No.5.May 2011, Page 304-308. [2] M.J.Schulte,E.E Swartzlander,Jr., Truncated multiplication with correction constant in VLSI Signal Processing VI.Piscataway,NJ: IEEE Press,1993,pp.388-396. [3] T.-B.Juang and S.-F.Hsiao, Low-error area efficient fixed-width multipliers with low-cost compensation circuits, IEEE Trans.Circuits Syst.I, reg.papers, vol.52, no.6, pp.299-303, Jun 2005. [4] C.S.Wallace, A suggestion for a fast multiplier, IEEE Trans.Electron.Comput.,vol.EC-13,no.1,pp.14-17,Feb 1964 [5] L.Dadda, Some schemes for a parallel multipliers, Alta Frequenza, vol.34, pp.349-356, 1965. [6] E. George Walters III, Mark G. Arnold, and Michael J. Schulte, Using Truncated multipliers in DCT and IDCT hardware accelerators. [7] Bhawana Tewari, Sonali Dubey, M.Nizamuddin Comparision analysis between DWT and DCT. [8] Archana Deshlahra, G. S.Shirnewar, Dr. A.K. Sahoo A Comparative Study of DCT, DWT & Hybrid (DCT-DWT) Transform. COMPARITIVE ANALYSIS OF IMAGE COMPRESSION TECHNIQUE (DWT) USING TRUNCATED MULTIPLIER Threshold PSNR value using conventional PSNR value using error efficient multiplier 86