E84 Lab 3: Transistor

E84 Lab 3: Transistor Cherie Ho and Siyi Hu April 18, 2016

Transistor Testing 1. Take screenshots of both the input and output characteristic plots observed on the semiconductor curve tracer with the following clear labeled (with meaningful increment): The voltage (horizontal axis) or V BE I C V CE The current (vertical axis) I B or For the output plot, each one of the 12 I B values in the family Figure 1: Input characteristic plot (Vertical 1mA increment) Figure 1 shows that V BE 0.7V when I B is greater than 1mA. Figure 2: Output characteristic plot

Determine the value β = I C /I B (also referred to as the ``forward transfer current ratio'' and denoted by h f or h FE on the 2N3904 datasheet (also see class notes ) from the output plot for each of the 5 transistors. From the output characteristic plot, β = ΔIB ΔI C = 1.9 ma 0.9 ma 0.01 ma 0.005 ma = 2 00. According to the datasheet, 70 < h f < 300 for I C 1 ma. Therefore, the β value calculated from Figure 2 is consistent with the datasheet value. Determine V BE from the input plot when I B is within the range of 0.01 to 0.1 ma, i.e., I C is within the range of 0.01β to 0.1β. Figure 3: Input characteristic plot (Vertical 0.1mA increment) Figure 3 shows that for I B in the range of 0.01 to 0.1 ma, V BE 0.6V. This is pretty close to V BE 0.7V when I B > 0.1 ma. We can still approximate V BE as 0.7V when I B is in the range of 0.01 to 0.1 ma to simplify calculation. Describe how the load line changes in the output plot when R C and V CC are increased or decreased.

Figure 4: Load line and output characteristic plot The light gray plots in Figure 4 are the output characteristic plots. The load lines are straight lines with slope vertical intersection and horizontal intersection. As Rc 1 R C V CC V CC increases, the slope of the load line is less negative as shown in the plot on the right. Similarly, as Rc decreases, the slope will be more negative. As Vcc increases, the slope of the load line stays the same, but the load line shifts to the right. That means as Vcc decreases, the load line shifts to the left. R C Transistor Circuit Construction 1. Design and build the voltage amplifier based on fixed biasing shown below. Determine the value of R B, R C, and V CC to achieve maximum voltage amplification and minimum distortion by setting the DC operating point to be in the middle of the linear range of the output characteristic plot. The values of capacitors C should be large enough so the impedance frequency ω. Z C = 1 /jωc can be assumed to be zero approximately for the signal

Figure 5: Transistor amplification circuit I We set V CC = 12V. For DC operating point, V in and R s can be ignored, since they only V CC V BE produce AC voltage. Assume V BE 0.7V, so I B = R = 11.3V. B RB Since the DC operating point is expected to be in the middle of the linear range of the output characteristic plot, we get I C = βi B = 200IB = 2260V R, so V R. B out = V CC I C C Given I C = 2260V and V out = 12V I C R C, we wanted to find R B and R C such that RB V out V CC /2 = 6 V. Although we wanted high R C values to increase the gain, we need to ensure I B is at least 0.1 ma so that the approximation V BE 0.7V still holds. We chose R B = 820kΩ, R C = 200Ω We used C = 10 μc and ω = 280 khz to achieve maximum gain. The impedance of the capacitor is Z C = ωc 1 = 0.36 Ω, which is negligible compared with the resistor values.

Figure 6: Transistor amplification circuit I (breadboard) Calculate the DC operating point on the output characteristic plot ( and ) based on I c V CE your design, and compare it to the actual one measured from the actual circuit. Using the equations derived earlier, we got I C = 2260V 820kΩ = 27.6 ma V CE = V out = 12V I C 200Ω = 6.49V We have measured the actual DC operating point from the circuit, and it was 6.29V. The difference in the results is likely due to our use of analog components which do not reflect ideal values we used to calculate the DC operating point and the linear approximation of the nonlinear component during calculation. Test the circuit by a sinusoidal signal of 50 mv peak to peak amplitude from signal generator (with output resistance R s = 50Ω) and an oscilloscope (with input resistance R in = 100MΩ ) to monitor the input and output signals both before and after the amplification and to observe the voltage gain and waveform distortion. Compare the predicted gain based on the small signal model with the actual one. For AC signal, the circuit diagram can be modified to Figure 7.

Figure 7: AC amplification circuit I V On the input side, the input resistance is R in = R B r be r be, since r be η T IB, where I B = V 0.7V cc R B R in and V T 0.026V, is a few hundred ohms and R B is in kω. Then r be v in v be = v in R +R = v, so. in s inr be+r i s b = v b r be r be+rs The output resistance is R out = R C R L R C, since R C is in kω and R L = 1 M. Then, v out = i c Rout = β ibrc = β v in R C. The AC gain is A = vin v out = β R C r +R be S r +R be s For the parameters used in this design problem, the expected gain is 168. The negative sign means there is a phase shift of 180. Figure 8: Output with Vpp = 50 mv Sinusoidal Input of 280 khz Input Vpp Output Vpp Experimental gain Expected gain 50 mv 5.71 V 114 168 The experimental gain measured is lower than expected. This is possibly due to the distortion as the DC operating point is not half of Vcc. It is most likely due to our use of analog components which do not reflect ideal values we used to calculate the DC operating point. Observe the polarity inversion and the signal distortion. Increase the amplitude of the input sinusoid from 50 mv to 1 V and observe the output in terms of the amount of distortion and clipping at both the positive and negative peaks of the sinusoid.

Figure 9: Output with Vpp = 1 V Sinusoidal Input of 280 khz (the top cursor is at 0V) From Figures 8 and 9, we see that there is more distortion and clipping for an input sinusoid of a larger amplitude. There is more clipping at 1V as the output amplitude is larger than at 50 mv and is higher than the threshold of the transistor. Distortion is caused if the AC component is too high, which means the transistor is not operating in the linear region. When the input sinusoid is higher, there is more distortion as the input is closer to the saturation or the limit of the transistor circuit. 2. Repeat the above for the amplifier based on a self biasing circuit shown in the figure below. Determine the values of R 1, R 2, R c, and R E to achieve maximum voltage amplification and minimum distortion by setting the DC operating point to be in the middle of the linear range of the output characteristic plot. Hint 1: To minimize distortion, the DC operating point should be around the center of the linear region of the output characteristic plot, i.e., V CE V cc/2. Hint 2: write a piece of Matlab code based on the equations for the self biasing circuit given here to calculates the DC operating point ( I B, I c, V B, V c, V E, and V CE = V C V E ), based on the circuit parameters V CC, R 1, R 2, R C and R E that you choose for your design.

Figure 10: Transistor amplification circuit II For the DC operating point, the capacitors are considered as open circuit. For the source side, using Thevenin s rule, V Th = R 2 1 2 V, R. Assume V BE = 0.7V, I B = V T h 0.7V (β+1)r +R E T h and R 1+R CC Th = R R 2 R +R β(v 0.7V ) T h I C = (β+1)r +R E T h Again, V CC = 12V. We needed V out V CE I C (R C + R E ) to be approximately /2 = 6V while making sure I B 1 2 is greater than 0.1 ma. Thus, we chose R 1 = 28kΩ, R 2 = 20kΩ, RC = 2 00Ω, RE = 2 40Ω. The capacitance was kept at 10μF. V CC Figure 11: Transistor amplification circuit II (breadboard)

Calculate the DC operating point on the output characteristic plot ( I C and V CE ) based on your design, and compare it to the actual one measured from the circuit. Substituting in the designed parameters, we get V Th = 200kΩ 200kΩ+24kΩ 1 2V = 1 0.71V I B = V T h 0.7V (β+1)r +R = 10.71 0.7V 201 240Ω+21.4kΩ = 0.138 ma E B I C = βi B = 200 0.138 ma = 28.7 ma V C = V out = V CC I C R C = 9.13V V E I C R E = 3.45V V CE = V C V E = 9.13V 3.45V = 5.68V V B = V E + V BE = 3.45V + 0.7V = 4.15V The measured DC operating point is around 6.1V. Again the difference might be caused by the uncertainties in the electrical components as well as the linear approximation of the nonlinear semiconductor component. The approximation is less accurate for this circuit than the previous circuit probably because there are more simplifications used in this case for linearizing semiconductor components and eliminating the impedance capacitors. Test the circuit by a sinusoidal signal of 50 mv peak to peak amplitude from signal generator and an oscilloscope monitor the input and output signals both before and after the amplification and to observe the voltage gain and waveform distortion. Compare the predicted gain based on the small signal model with the actual one. Figure 12: AC amplification circuit II The AC amplification of this circuit is similar to the previous circuit. The same derivation and approximation method can be used so that the approximated AC gain is the same. A = vin v out = β R C = 168 r +R be S

Figure 13: Output with Vpp = 50 mv Sinusoidal Input of 280 khz (the top cursor is at 0V) From Figure 13, the output voltage has a voltage gain of 60.6 and a slight distortion where the maximum at 1.37V and the minimum at 1.68V. The shape of the output signal still resembles the input sinusoid. Observe the voltage gain as a function of the by pass capacitor in parallel with R E, and the capacitors at both the input and output ports, by trying different C values. Input capacitor ( μf ) Output capacitor ( μf ) By pass capacitor ( μf ) Output Vpp (V) Gain 10 10 10 3.08 61.6 10 10 100 3.03 60.6 10 10 10^ 4 6.94 138.8 10^ 4 10 10 0.014 0.28 100 10 10 1.31 26.2 10 100 10 3.94 78.8 10 10^ 4 10 1.85 37 There are several trends that can be observed from the above table. When the capacitance of the bypass capacitor decreases, the gain increases. When the

capacitance of the output capacitor increases, the gain also increases. The trend of the input capacitor is interesting. We expect the gain to be larger when the capacitance of the input capacitor increases. However, when the input capacitor is 100, the gain is 26.2 which is much lower than the gain at 10. This may suggest the relationship between the input capacitor and gain is not linear. Observe the voltage gain as a function of the signal frequency. Generate a Bode plot of the magnitude of the voltage gain for the frequency range of 10 Hz to 1 MHz. Find the maximum voltage gain and the frequency range in which this maximum gain is A max achieved. Frequency Output Vpp (V) Gain 280 khz (maximum Amax) 3.08 61.6 10Hz 0.10 2 100 Hz 0.10 2 1 khz 0.70 14 10 khz 2.63 52.6 100 khz 2.93 58.6 1000 khz 2.83 56.6

Figure 14: Bode Plot of Amplification Circuit Gain vs. Frequency The bode plot above shows that the frequency range at which there is maximum gain is between 100kHz to 600kHz. From the bode plot, we can see when the frequency is low, the gain is greatly attenuated, this is due to the high impedance of the capacitors which causes some voltage drop. This is ignored during our calculation. The maximum voltage gain is 61.6, which is at 280 khz. At very high frequencies, the transistor behavior is nonideal, so the amplification will be lower than expected. Observe the polarity inversion and the signal distortion. Increase the amplitude of the input sinusoid from 50 mv to 1 V and observe the output in terms of the amount of distortion and clipping at both the positive and negative peaks of the sinusoid.

Figure 15: Output with Vpp = 1 V Sinusoidal Input of 280 khz (the top cursor is at 0V) From Figure 13 and 15, the output signal of Vpp = 1V has more clipping and more distortion. When Vpp = 50mV, the output signal is relatively centered and there is no clipping, as the maximum and minimum are within the sensor range. For Vpp=1V, there is more clipping as the output range is above the sensor range. Additionally, there is more distortion for a larger AC input signal. Similar to circuit I, this is because the circuit is not operating in the linear region. Distortion occurs when the input is close to the saturation or limit of amplification. 3. Connect a load resistor R L to the amplification circuit above, measure the output voltage across R L as its value varies from 1 MΩ to 10Ω in decade scale. Then build an emitter follower as shown below and insert it in between the amplification circuit and the load R L. Re measure the output voltage across when its values varies as before. Explain R L what you observe.

Figure 16: Actual Emitter Follower Circuit Amplification Circuit: R L Output Vpp (V) Gain 10 Ω 0.22 4.4 100 Ω 1.35 27 1 kω 3.24 64.8 10 kω 3.86 77.2 100 kω 3.90 78 1 MΩ 3.94 78.8 For the amplification circuit, as the load resistance increases, the gain also increases. This is expected as the load resistor affects the voltage gain of the amplifier by drawing current from the transistor circuit. When the load resistor is larger, the voltage output is larger.

Figure 17: Emitter Follower Circuit Figure 18: Output of Emitter Follower Circuit with a 50mV input

Emitter Follower Circuit: R L Output Vpp (V) Gain 10 Ω 4.98 99.6 100 Ω 4.62 92.4 1 kω 4.02 80.4 10 kω 3.70 74 100 kω 3.72 74.4 1 MΩ 3.70 74 For the emitter follower circuit, the gain does not change a lot and is much (74 to 99.6) and is higher than the gain without the emitter follower circuit for the given range of load resistance. This is as expected because an emitter follower tries to keep the output voltage relatively constant, acting as a buffer. Also, we found the output gain decreases as load increases. This does not make sense. From Figure 18, the output shape of the emitter circuit is quite irregular, not sinusoidal. We believe this is caused by loose connection in the circuit. This problem is more significant when the load is high and the current through the load is small. Due to the size of the circuit, we could not improve the circuit, but we expect the gain to be more constant for different load resistance or higher for larger load resistance.