Fault Modeling and Analysis for FinFET SRAM Arrays

Fault Modeling and Analysis for FinFET SRAM Arrays A thesis submitted to the Division of Research and Advanced Studies of the University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in the School of Electronic and Computing Systems of the College of Engineering and Applied Sciences February 21, 2013 by Rathna Keerthi Meenakshi Siddharthan BE ECE, Anna University, 2009 Thesis Advisor and Committee Chair: Dr. Wen Ben Jone

Abstract IC industry is now undergoing a radical change from traditional planar MOSFET transistors to 3-dimensional FinFETs. Unlike planar MOSFETs, FinFETs offer an excellent short channel behavior and enables scaling of transistors to continue further. Also, they offer circuit designers a unique way of balancing performance and leakage power consumption by way of their dual gate structure that allows to alter their threshold voltage dynamically. Due to their three dimensional structure and very high packing density, it is unclear if traditional MOSFET fault models are adequate to model defects in FinFETs. In particular, fault behavior of FinFET-based SRAMs need to be studied, given the predominant increase of area occupied by memories in modern ICs. In this research, we model all possible spot defects in FinFET-based SRAM and their faulty behaviors are simulated in Hspice. The resulting electrical faults are transformed into functional fault models. Three new fault models are found and a march algorithm is developed to detect them efficiently. i

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Acknowledgments I wish to thank, first and foremost, my professor Dr. Wen Ben Jone for his guidance, constant encouragement and good advice. He was always there whenever I got stuck up with something. Thank you Dr. Jone, for all your help and concern. I would like to thank Dr. Ranga Vemuri and Dr. Carla Purdy for agreeing to be on my thesis committee and also for spending time to read this thesis. I would like to thank all my lab mates who helped to shape my thesis in a better way. Special thanks to Jianghao Guo and Qiang Han for their valuable suggestions. I should definitely thank my room mates Karthikeyan Muthalagu, Manoj Chakkaravarthy, Karthick Padmanabhan and Madhan Mohan Raju for making my life as a graduate student more enjoyable and supporting me at times of distress. I would also like to express my humble thanks to Vignesh Subbian whose advises are invaluable. Finally, I would like to thank my parents, sister and my brother-in-law for their invaluable love and support. iii

Contents 1 Introduction 1 1.1 MOSFET Power Crisis..................................... 1 1.2 Short Channel Effects...................................... 4 1.3 FinFETs - Successor of MOSFET............................... 5 1.4 Importance of Memory Testing................................. 7 1.5 Research Objectives and Thesis Organization......................... 8 2 Background 9 2.1 Multi-Gate devices....................................... 9 2.2 FinFET: Device Structure.................................... 12 2.3 FinFET: Device Characteristics................................. 15 2.4 FinFET Advantages....................................... 18 2.5 Memory Testing......................................... 18 2.5.1 Fault Modeling..................................... 18 2.5.2 Spot Defects...................................... 20 2.5.3 Memory Test Algorithms and Validation........................ 21 3 FinFET Based SRAM Design 23 3.1 SRAM Basics.......................................... 23 3.2 FinFET SRAM Advantages and Challenges.......................... 26 3.3 FinFET based SRAM Design.................................. 27 3.3.1 Fin Surface Orientation................................. 28 iv

CONTENTS 3.3.2 6-T SRAM Design................................... 30 3.3.3 6-T SRAM Design with Dynamic Feed back..................... 31 3.4 FinFET SRAM Electrical Schematic.............................. 34 4 Fault Modeling 38 4.1 Introduction........................................... 38 4.1.1 Definition and location of opens............................ 38 4.1.2 Definition and location of shorts............................ 40 4.1.3 Definition and location of bridges........................... 41 4.2 Primitives for Driving the Simulator.............................. 42 4.3 FinFET-based SRAM Fault Modeling............................. 45 4.4 Simulation Results....................................... 46 4.5 Functional Fault Models.................................... 51 4.5.1 The FFM1 Fault Class................................. 51 4.5.2 The FFM2 Fault Class................................. 52 4.6 Cuts on the fins of FinFET................................... 58 4.7 March Algorithm........................................ 59 5 Conclusions & Future Research 61 v

List of Figures 1.1 Subthreshold slope of CMOS transistor............................ 2 1.2 Supply voltage, feature size and power density scaling of CMOS............... 3 1.3 CMOS energy/operation vs Supply voltage Vdd........................ 4 1.4 Intel 3-D transistor structure and picture............................ 6 1.5 Transistor gate delay vs supply voltage Vdd.......................... 7 1.6 ITRS roadmap: area occupied by memories in SoC...................... 8 2.1 Effect of electric field lines from source and drain on the channel region in different types of MOSFETs.......................................... 10 2.2 Examples of double-gate MOS structures........................... 11 2.3 Different Gate Structures.................................... 11 2.4 FinFET device structure..................................... 12 2.5 FinFET device structure with three fingers........................... 14 2.6 Layout comparison between a planar MOSFET and a typical FinFET with three fins..... 15 2.7 SG and IG mode FinFET.................................... 15 2.8 FinFET - three modes of operation............................... 16 2.9 Simulated I ds Vs V gfs for n-type FinFET........................... 17 2.10 SRAM memory cell....................................... 20 2.11 Memory fault simulation.................................... 22 3.1 Mainstream MOSFET based 6-T SRAM cell......................... 25 3.2 Butterfly plot to measure SNM of SRAM cell......................... 26 vi

LIST OF FIGURES 3.3 FinFET device structure..................................... 28 3.4 FinFET SRAM simulation parameters............................. 29 3.5 A 3-D schematic view of FinFET 6-T SRAM cell....................... 29 3.6 Silicon wafer showing different orientation of transistors................... 30 3.7 6-T FinFET SRAM schematic and layout with 1-fin in NPD................. 31 3.8 6-T SRAM layout of 2-fin NPD and rotated fin NPD..................... 31 3.9 Butterfly graphs of different 6-T SRAM designs........................ 32 3.10 FinFET 6-T SRAM design with feed back........................... 33 3.11 Leakage, SNM of different FinFET SRAM designs...................... 33 3.12 FinFET-based SRAM electrical schematic........................... 35 3.13 Control signal timing for a write................................ 36 3.14 Control signal timing for a read................................. 37 4.1 Open defect in a metal..................................... 39 4.2 Open defects in FinFET SRAM cell.............................. 40 4.3 Four cell configuration..................................... 42 4.4 Fault modeling architecture................................... 42 4.5 Defect free FinFET SRAM simulation............................. 44 4.6 Multi-cell transition coupling fault model........................... 54 4.7 Simulation result for CF trm................................... 54 4.8 Incorrect read coupling fault model............................... 55 4.9 Simulation result of CF irm................................... 56 4.10 Three-cell disturb coupling fault model............................ 56 4.11 Simulation result of CF dsm................................... 57 vii

List of Tables 4.1 List of opens.......................................... 40 4.2 List of shorts.......................................... 41 4.3 List of bridges within a cell................................... 41 4.4 List of bridges between adjacent cells............................. 41 4.5 Operation simulation...................................... 43 4.6 Data retention simulation.................................... 43 4.7 Simulation results for resistive open defects in a cell...................... 47 4.8 Simulation results for full open defects on the back gate of FinFET transistor........ 48 4.9 Simulation results for shorts within a cell........................... 48 4.10 Simulation results for bridge defects within a cell....................... 49 4.11 Simulation results for bridge defects between cells in the same row.............. 49 4.12 Simulation results for bridge defects between cells in the same column............ 50 4.13 Simulation results for bridge defects between cells in the diagonal.............. 50 4.14 Modified march SR algorithm................................. 60 viii

Chapter 1 Introduction Invention of Integrated Circuits (ICs) has enabled the rapid development of modern semiconductor industry for more than 40 years. Constant innovations in this field have yielded dramatic improvements in product performance, cost and size making modern electronic products more capable and affordable to consumers. The IC industry s rapid growth was fueled mainly by the continuous scaling of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which is considered as the building block to construct integrated circuits. 1.1 MOSFET Power Crisis Since the 1960s, planar MOSFET transistor dimensions have been decreasing as predicted by the well known Moores law [1]. Decreasing the device dimensions has improved the transistor speed and density in the following ways [2]: a) chips operating frequency is increased, allowing for faster circuits; b) higher packing density (because of the reduction in size of individual transistor) reduces the cost of ICs; c) scaling voltage reduces the power consumption but increased transistor density offsets the power gain, thereby maintaining a constant power density. The lower energy/switching event exactly matched the increased energy by having more gates and having them switch faster, so in theory the power density would stay constant. Recently, full chip power density has been increasing as a result of non-scaling of power supply voltage Vdd. The fundamental issue is that MOSFET transistors are not perfect switches. They leak when they are turned off. Figure 1.1 shows the subthreshold slope Id (log scale) vs Vgs of a CMOS transistor. Below the threshold voltage V th, the current decreases gradually and does not go to zero. As seen there is a certain 1

CHAPTER 1. INTRODUCTION 1.1. MOSFET POWER CRISIS Figure 1.1: Subthreshold slope of CMOS transistor [3] off current flowing between the source and drain when the transistor is turned off. The subthreshold swing S is defined as the inverse slope of the log(id) vs Vgs characteristics in the subthreshold region. The value of the leakage current depends on this slope or S value. The steeper the curve is, the better will be the leakage savings. Its unit is is mv/decade. The leakage current is set by the transistor s threshold voltage V th and there is a limit in how low one can make a transistor s V th. Low V th provides high current flow thereby the circuit switches faster. But it also moves the subthreshold curve to the left resulting in increased leakage power. Basically leakage current specification for a design sets the limit of V th. There is a fundamental trade-off between performance and leakage power. So with V th fixed, changing Vdd simply trades off energy and performance. Figure 1.2 uses microprocessor data to track CMOS technology scaling since 1980 to today [4]. It plots technology feature size, Vdd and power consumption vs time. Through four technology generations, from 2µm to 0.5µm in mid 1990 s, the power savings were large enough that Vdd did not scale and was kept constant at 5V. As power density started to increase with further scaling, Vdd was also scaled until 130nm technology. Power density increased 30X during this period mainly due to the increase in performance optimization ( e.g., improved circuit design, sizing constraints and deeper pipeline) that were applied to the chips. The chip s operating frequency was also aggressively scaled by about 2X/generation, which caused the power density to exponentially rise. At some point of time because of this power issue, CMOS IC industry stopped both increasing in die size and frequency scaling [4]. 2

CHAPTER 1. INTRODUCTION 1.1. MOSFET POWER CRISIS Figure 1.2: Microprocessor Vdd, Power/10, and feature size versus year (from 1994 to today Vdd has roughly tracked feature size) [4] Figure 1.3 plots the CMOS energy/operation to supply voltage Vdd [5]. As supply voltage is scaled down, dynamic energy gets reduced exponentially whereas the circuit delay increases. Also, leakage energy increases with scaling down of supply voltage. As shown in the figure, CMOS has a fundamental lower limit in energy/operation due to sub-threshold leakage. There is no gain in scaling down when the total energy increases offsetting the benefit of scaling. This was the primary reason behind IC industry to implemented architectural performance techniques like multi-cores and multiple threads that exploit parallelism to improve the overall chip performance, while maintaining the chip power density and total chip power dissipation at an acceptable level [5]. MOSFETs power issue is a major road block for scaling trend and also as Lg decreases for each technology node, short channel effects (SCE) and process induced variations on V th impedes further scaling. We discuss the SCE effects and process induced variations briefly in the next section. 3

CHAPTER 1. INTRODUCTION 1.2. SHORT CHANNEL EFFECTS Figure 1.3: CMOS energy/operation vs supply voltage Vdd [5] 1.2 Short Channel Effects When the gate length Lg is scaled down, short channel device has channel length comparable to depth of drain and source junctions and depletion width. It causes a significant departure from the normal characteristics of the transistor known as short shannel sffects (SCE). It causes threshold voltage V th variation and sub-threshold conduction (leakage). The current flow between source and drain in the channel strongly depends on the formation of an inversion layer based on the gate voltage bias voltage V GS. If this bias voltage is below the threshold voltage (V Gs < V th ), the electrons (carrier) in the channel surface face a potential barrier which stops them from flowing between source and drain. But when gate voltage is increased above the threshold voltage, this barrier is reduced so that current starts to flow. In short channel devices, the potential barrier is controlled by both gate voltage V Gs and drain-to-source voltage V DS. As V DS is increased, it reduces the potential barrier in the channel thereby leading to drain induced barrier lowering (DIBL). To maintain the strong gate control of the channel potential in bulk devices, various technological innovations such as ultra-shallow source/drain junctions, ultra-thin gate dielectrics, halo implants and advanced channel dopant profile engineering techniques such as super-steep retrograde wells have been necessary. Each of these techniques is now approaching fundamental physical limitations which in turn, limits further scaling of device dimensions [2]. In planar transistors, the gate di-electric thickness is the most important dimension to enable scaling and it has been scaled aggressively over the years. A thin di-electric will increase the control of the gate 4

CHAPTER 1. INTRODUCTION 1.3. FINFETS - SUCCESSOR OF MOSFET voltage over the channel and reduces the source/drain influence. It also helps to achieve larger ON current. However, gate di-electrics are already so thin that their further scaling results in electrons tunneling through them increasing the leakage currents [2]. In order to continue scaling of MOSFETs, heavy body doping is done to eliminate leakage paths far from the gate di-electric surface. Halo doping is performed to suppress sub-surface leakage, but this tends to increase the channel doping in small channel devices. Increased channel doping concentration reduces the carrier mobility due to impurity scattering, enhances band to band tunneling leakage and increases depletion and junction capacitances [2]. This contributes to reduced device performance. In Summary, designers face several challenges in continuing scaling of MOSFETs. Fixing one leads to another new problem which makes MOSFET scaling an increasingly harder one with each technology node. Control of critical dimensions such as Lg continues to be difficult as the physical gate length is considerably smaller than the lithography printed line width [2]. Controlling the lithography with further scaling of Lg becomes very difficult. While advanced process control techniques can control the process induced variations, the role of random dopant fluctuations (RDF) and line edge roughness (LER) are expected to increase, so that these variations will affect the chip s power dissipation and performance [6]. Hence, new transistor structures which has better immunity to process variations and devices with tunable V th are beneficial to overcome variations in transistor characteristics. 1.3 FinFETs - Successor of MOSFET The previous sections highlighted the need for new device structures which suppress the off-state leakage as Lg is scaled down. This will allow for reduction in V th and hence supply voltage Vdd. FinFETs [7] shows such a characteristics that will help the IC industry to to move forward with the scaling trend for at least 5-6 years. In May 2011, Intel announced that they will be moving on to the 3-D Trigate Transistor Technology for their microprocessors at 22nm node [8]. MOSFETs dominated the IC industry for more than two decades now, so this announcement from Intel came as most radical change in the transistor design. A 3-D transistor looks much the same as a planar transistor, but instead of planar inversion layer (channel), the channel is raised above in the third dimension and the gate is made to wrap around it. This gives the gate an excellent electrostatic control over the channel (see Figure 1.4). It took Intel around 10 years to develop the 5

CHAPTER 1. INTRODUCTION 1.3. FINFETS - SUCCESSOR OF MOSFET Figure 1.4: Intel 3-D transistor structure and picture (image courtesy Intel Corporation) [9] technology for full volume production. As shown in Figure 1.5, Intel reports that its new 3D, 22nm transistors are 37% faster at low voltage compared to Intel s current 32nm planar transistors, making them better for smartphones and other handheld devices. At higher voltage (1V) the new transistors are 18% faster than 32nm planar. They draw less than half the power as Intel s 32nm chips. Recently, the leading chip makers Global Foundries, Samsung, Taiwan Semiconductor Manufacturing Co. (TSMC), and United Microelectronics Co. (UMC) have all made it clear that they plan to pursue the FinFET technology [10]. They target to introduce FinFETs at the 14nm manufacturing process node, a step more or less behind Intel s 22-nm introduction. It is estimated that it will cost the foundries and their partners about 6 billion US$ to develop the manufacturing process and the computational tools needed to design 14-nm and 16-nm chips [10]. So, FinFETs are all set to take over the IC industry from the decade old work horse MOSFETs. 6

CHAPTER 1. INTRODUCTION 1.4. IMPORTANCE OF MEMORY TESTING Figure 1.5: Transistor gate delay vs supply voltage Vdd (image courtesy Intel Corporation) [9] 1.4 Importance of Memory Testing With the advent of system on chip (SoC), area occupied by memories has been rapidly increasing. System performance is strictly related to the size and speed of the memory. Figure 1.6 shows the international technology road map for semiconductors (ITRS) forecast that in 2014 more than 94% of the SoC area will be composed of memories [11]. Moreover, memories are often designed with a density that is at the extremes of the process technology making them susceptible to manufacturing defects. Thus manufacturing test of memories plays an important role in the final product cost. Effective test solutions will help improve the yield of the chip especially with the rapid evolution in the new device structures and process technologies. Functional fault models are usually defined for memory testing. They define the behavior of the faulty memory. Fault models are continuously proposed to cover defects and failures in deep sub-micron process technologies. 7

CHAPTER 1. INTRODUCTION 1.5. RESEARCH OBJECTIVES AND THESIS ORGANIZATION Figure 1.6: ITRS roadmap: area occupied by memories in SoC [11] 1.5 Research Objectives and Thesis Organization According to ITRS, the reliability and testing of the new devices and structures will be a challenge in the near future (2011-2018) [12]. In this research, we study the behavior of FinFET-based SRAM cell in the presence of spot defects at all possible locations, and the corresponding fault models are derived based on Hspice simulation results. Three new fault models are found. To the best of our knowledge, this is the first work on fault modeling of FinFET SRAM cell. For Hspice simulation, we use the predictive technology model (PTM) for 20nm multi-gate transistor [13]. In Chapter 2, we give a brief introduction on the FinFET device structure, characteristics and its challenges. We also discuss basics of memory testing. FinFET-based SRAM design is discussed in detail in Chapter 3. We highlight scaling issues of the MOS- FET SRAM cell as well as advantages of the FinFET SRAM. Finally we discuss the electrical schematic of the SRAM that we use to do fault modeling. In Chapter 4, we discuss the fault modeling approach, new fault behaviors and the classification of the fault models based on Hspice simulation results. Finally, in Chapter 5 we conclude our results and suggestions for further continuation of this work are given. 8

Chapter 2 Background The main drawbacks in MOSFET scaling can be attributed to the increasing power density, short channel effects and process induced variations in the transistor characteristics. FinFETs offer an excellent channel control thereby reducing the short channel effects which in turn allows its scaling to sub-10nm regime. In this chapter, we briefly discuss multi-gate devices, FinFET fabrication, device structure and its circuit characteristics. Finally, we give a short introduction to memory testing fundamentals and spot defects in SRAM cells. 2.1 Multi-Gate devices As the dimension of transistors shrinks, the proximity of source and drain causes short channel effects which hamper the further scaling transistors. The control of a channel by its gate is affected by the electric field lines from the source/drain. This is shown graphically in Figure 2.1. It seems impossible to scale planar transistors below 20nm node [14]. Other device architectures such as fully depleted SOI (FDSOI) are proposed in the literature. Short channel effects are reduced by using a very thin burried oxide and an underlying ground plane (Figure 2.1 (C)). It has the disadvantage of increased junction capacitance and body effect [15]. A more efficient way to control short channel effects can be obtained using a double gate transistor structure as shown in Figure 2.2(D). In a double gate device, both gates are connected together. The electric field from the source and drain terminate on the bottom gate electrode and cannot influence the channel 9

CHAPTER 2. BACKGROUND 2.1. MULTI-GATE DEVICES Figure 2.1: Effect of electric field lines from source and drain on the channel region in different types of MOSFETs [14] region. Only the field lines that propagate through the channel can affect the channel region. This can be easily reduced by decreasing the silicon film thickness. The first article on this double gate structure was published in 1984 by [16]. The first implementation of double gate SOI MOSFET was fully depleted leanchannel transistor (DELTA) [17] where the device was made of a narrow silicon channel called finger or fin as shown in Figure 2.2(A). The FinFET device was published by [7] which was similar to DELTA except for the presence of di-electric layer on top of the silicon fin (Figure 2.2(B)). Other implementations based on different gate structures such as gate all around device, surrounded gate, triple gate are shown in Figure 2.3. Intel calls its new transistor as tri-gate since the gate covers all the three sides of the fin. In Intel s FinFET design, the fin has an unusual shape of a triangle rather than a rectangle which might be due to the fact that triangle has a higher structural strength and can be more reliably manufactured [18]. 10

CHAPTER 2. BACKGROUND 2.1. MULTI-GATE DEVICES Figure 2.2: Examples of double-gate MOS structure: (A) DELTA MOSFET, (B) FinFET [14] Figure 2.3: Different gate structures [14] 11

CHAPTER 2. BACKGROUND 2.2. FINFET: DEVICE STRUCTURE 2.2 FinFET: Device Structure Multi-gate MOSFETs are considered as a promising solution to continue the scaling trend. As illustrated in Figure 2.4, FinFET is a device in which a thin fin-shaped body is straddled by the gate forming two self Figure 2.4: FinFET device structure [19] 12

CHAPTER 2. BACKGROUND 2.2. FINFET: DEVICE STRUCTURE aligned channels that run along the sides of the fin. Such a gate can fully deplete the channels of carriers. This results in better electrostatic control of the gate over the channel. Also, thin body of the fin is the requirement to ensure that the straddled gate has complete control of the channel. Though the gate protrudes out of the wafer plane, current flows in a plane parallel to the wafer plane, making the FinFET a quasi-planar structure. The other double gate structures are very difficult to fabricate. FinFETs have an added advantage of process simplicity and compatibility with conventional planar CMOS technology. Every process step used to fabricate FinFET are in widespread use today. A gate can also be fabricated on top of the fin, in which case it is a triple gate FET. Or optionally, it can be removed by making the gate oxide thick so that the channel is formed only in the sides of the fin. As seen in Figure 2.4, the critical geometric parameters of a FinFET are defined below: L Gate : physical gate length of FinFET defined by the spacer gap H F in : height of silicon fin, defined by the distance between top gate and buried oxide T F in : thickness of silicon fin, defined by the distance between front and back gate oxides P F in : the fin pitch is the spacing between the fins plus the fin width. It is the minimum pitch allowed between adjacent fins by lithography at a particular technology node. W : geometrical channel width defined as W = 2H F IN + T F IN (2.1) This is because W as defined above is indeed the width of the gate region that covers the channel in the fin. This can be understood easily if one unfolds the gate (unwrap it). The width definition is for a triple gate FinFET. If the gate above the fin is absent (by using heavier gate oxide), then the T F in term in 2.1 is taken out. The channel width in FinFETs are quantized, and the individual fins of a FinFET transistor have the same thickness and height. As a result, current drive is fixed to a single discrete value for a given gate length. To drive larger current, multi-fin devices are used. The current drive of a multi-fin FinFET is equal to the current drive of one fin multiplied by the total number of fins. Figure 2.5 shows a FinFET using three 13

CHAPTER 2. BACKGROUND 2.2. FINFET: DEVICE STRUCTURE Figure 2.5: FinFET device structure with three fingers [22] fins. Thus, with this structure a three times higher drive current can be achieved. The gate comb is formed as a small stripe which contacts the gates of all fins. On the surface, increasing the height of the fin (H F in ) is a much desired capability since it lets one increase the device width W without increasing the planar layout area (increasing W increases I on, a desirable feature). However, there is a definite range (in relation to T F in ) beyond which H F in should not be increased; otherwise, one encounters short channel effects [20] [21]. Also, the minimum feature size in FinFET is its fin width or thickness (T F in ) and not gate length (L Gate ) [14]. Schematic layouts of a conventional planar MOSFET and a FinFET with three fins are compared in Figure 2.6. In FinFETs, exactly one fin can be placed in one P F in. Hence the value of P F in determines the layout area and it is limited by source/drain tilt angle. 14

CHAPTER 2. BACKGROUND 2.3. FINFET: DEVICE CHARACTERISTICS Figure 2.6: Layout comparison between a planar MOSFET and a typical FinFET with three fins 2.3 FinFET: Device Characteristics As seen in the previous section, FinFET devices come in many flavors. In shorted-gate (SG) FinFETs, both gates are connected together such that it can serve as a direct replacement for conventional bulk-cmos devices. In independent gate FinFET (IG), the top part of the gate is completely etched away such that two gates can control the channel independently. This mode offers more options for digital designers, as one gate can be used to drive the transistor while the other one can control the threshold voltage. Figure 2.7 shows both SG and IG FinFETs. From structural perspective, FinFETs offer SG and IG modes but from design perspective, it offers an additional low power mode (LP). In LP mode, the back gate is reverse biased to reduce sub-threshold leakage current. Figure 2.8 shows the circuit diagram of the three modes of FinFETs. The ideal reverse bias voltages for n-type and p-type FinFETs are calculated to be -0.26V and 1.18V respectively [23]. Figure 2.7: (a) SG mode FinFET (b) IG mode FinFET [23] 15

CHAPTER 2. BACKGROUND 2.3. FINFET: DEVICE CHARACTERISTICS Figure 2.8: FinFET - three modes of operation Figure 2.9 shows the SPICE simulated DC transfer characteristics, I ds Vs V gfs for a 32nm n-type Fin- FET [23]. Here V gfs denotes the voltage between the front gate and source whereas V gbs is the voltage between the back gate and ground. The transistor s source was tied to ground and the drain to the supply voltage. Transfer characteristics are obtained for various back gate voltages V gbs. Power supply was fixed at 1V. Characteristics corresponding to SG, LP and IG modes of operation are indicated. Similar kind of characteristic can be obtained for p-type FinFET. From this figure, we can observe variations in the on and off state FinFET currents I on and I off. The following conclusions can be drawn [23]: FinFETs offer the best drive strength in SG mode. I on reduces about 60% in IG and LP modes. Disabling one gate (V gbs ) results in reduced I on. Applying reverse bias voltage on the back gate further reduces I on. I off or leakage current decreases more rapidly with increasing reverse bias. 16

CHAPTER 2. BACKGROUND 2.3. FINFET: DEVICE CHARACTERISTICS Figure 2.9: Simulated I ds Vs V gfs for n-type FinFET [23] 17

CHAPTER 2. BACKGROUND 2.4. FINFET ADVANTAGES 2.4 FinFET Advantages By means of superior electrostatic behavior obtained from their three dimensional structure, FinFETs offer several advantages over their planar counterparts including (but not limited to) [24]: Excellent control of the channel by the gate. The inversion layer can be chopped off more easily. FinFETs have a near ideal sub-threshold behavior which was very difficult to achieve in planar MOSFETs. Greatly reduced short channel effects. FinFETs are slated to scaled down to 7nm node in the future. The fin shaped body along with the increased control of the gate makes this possible. Very high integration density because of its three dimensional structure. Very low variability due to doping free channels. The body of the fin is very lightly doped, reducing the effect of random dopant fluctuations. With the above advantages, FinFET broadens the design window once again such that operating voltage can now be scaled down thereby reducing both dynamic and static power consumption. For memory designers, FinFETs offer significantly lower retention voltage requirements for SRAMs compared to planar transistors. Finally, a major design optimization benefit of FinFET compared to planar transistor is much higher performance at the same power, or equal performance at a much lower power. This essentially gives the circuit designers the flexibility to design for low power battery-powered devices. 2.5 Memory Testing 2.5.1 Fault Modeling In Chapter 1 we discussed that memories will occupy about 94% of area of an IC in the future. Due to this enormous usage, any improvement in their design like reducing energy consumption or reducing the cost will directly reflect on systems they are integrated in. This continuous research to improve the memory density pushed them to their limits, making modern memories extremely susceptible to physical defects 18

CHAPTER 2. BACKGROUND 2.5. MEMORY TESTING and environmental influences that may severely compromise their correct behavior. Therefore, efficient and detailed testing of memory components is mandatory. A complete SRAM test must guarantee the correct functionality of each cell of the memory in the worst condition with regard to voltage constraints and timing requirements. Functional tests are widely used to test SRAM [25]. It is done by applying a set of operations (read and erite) to the SRAM under test and observing the faulty behavior with respect to the expected good behavior. Faulty behavior may be caused due to defects. Defects during fabrication often consists of dust particles. An error is the observable manifestation of a defect. Such defects at layout level are translated to electrical faults and then into logical faults so that they can be tested. This mapping of defects from electrical faults into logical faults is called fault modeling. Formal way to represent functional faults of a memory is called fault primitive (FP). A FP is a formal notation used to describe the faulty behavior of SRAM memory cell. <S/F/R>: denotes a FP involving a single cell. S describes the sensitizing operation; S ε {0, 1, w0, w1, w, w, r0, r1, }, where 0 denotes logic 0, 1 denotes logic 1, w0 (w1) denotes write 0 (write 1) operation, w (w ) denotes an up transition (down transition) write operation. represents any operation. ε {0, 1, w1, w0, w, w, r1, r0}. If the fault effect takes place after some time T, then the sensitizing operation is given as S T. < S a ; S v /F/R > a,v : denotes a FP involving two cells: S a describes the sensitizing operation or state of the aggressor cell whereas S v represents sensitizing operation or state of the victim cell. The aggressor cell (denoted by a ) is the cell sensitizing a fault in another cell called the v-cell (denoted by v ). In both notations, F denotes the faulty behavior of the cell. F ε {0, 1,,,?} where ( ) represents up (down) transition operation and? represents undefined logical value. R denotes the logical value which appears at the output of the SRAM. If the sensitizing operation is a read/write, then R ε { 0, 1,?, - }. A - in R means that the output is not applicable in that case. For example, if S= w0, then no data appears at the output and hence R is replaced by -. The fault effect can also be strong or weak: Strong fault: memory faults which are fully sensitized by any operation; i.e., a read or write operation 19

CHAPTER 2. BACKGROUND 2.5. MEMORY TESTING Figure 2.10: SRAM memory cell [25] fails. Weak fault (wf): memory faults which are partially sensitized by an operation; for example, a defect that causes slight disturbance to the voltage of the true node but does not make the cell change its state. In the presence of a weak fault, the cell functions properly. 2.5.2 Spot Defects Majority of faults in SRAM circuits are due to undesired particles called spot defects (SD). They have the following electrical effects: Open - extra resistance within a connection. The resistance value R op is given by 0 < R op. When R op =, it represents a complete open. Short - an undesired resistive path between a node and the supply or ground. The resistance value R sh is given by 0 < R sh. When R sh = 0, it represents a complete short. Bridge - parallel resistance between two signal nodes. A bridge can be within a cell or between two cells. The resistance value R br is given by 0 < R br. Many defects can be identified in an SRAM (refer figure 2.10), but due to its symmetric nature, only a subset of them need to be simulated. The complementary faults do not need to be simulated and can be easily derived. Complementary fault terminology is explained below [26]: Fault SD1 is complementary to fault SD2, if SD1 exhibits the same behavior as SD2, with the only difference that logic 0 is replaced by logic 1 and vice versa. For example, if for SD1 a r1 operation causes an up-transition in the cell, then for SD2 a r0 operation causes a down-transition in the cell. 20

CHAPTER 2. BACKGROUND 2.5. MEMORY TESTING Fault SD1 is reversed to fault SD2 if it exhibits the same behavior as SD2, with the only difference that the aggressor cell and victim cell are exchanged. Fault SD1 is reverse complementary to fault SD2, if SD1 is reversed to fault SD3, and SD3 is complementary to SD2. An asymmetric fault makes the SRAM circuit asymmetric. For example, the fault whereby node T in Figure 2.10 is shorted. An asymmetric fault is always complementary to another asymmetric fault. A symmetric fault is a fault which makes the SRAM circuit symmetric. For example, consider an open in the V cc path to both P-FinFETs in Figure 2.10. A symmetric fault has no complementary fault. 2.5.3 Memory Test Algorithms and Validation First proposed memory tests in the literature were ad-hoc algorithms. They were developed without the formal fault models and proofs. The main drawback were high complexity and generally not linear with respect to memory size. To overcome the complexity issues, march tests have been introduced [25]. March test is a test algorithm composed of sequence of march elements. Each march element (ME) is a sequence of memory operations applied sequentially on a certain memory cell. The way in which the sequences are moved from one cell to another cell is called address order. The address order can be an increasing ( ) or decreasing ( ) one. is used when the order is irrelevant. In general, the complexity of march test is in the order of O(N), linear with respect to the size of the memory array under test. The main phase of memory testing is to define comprehensive fault models able to carefully represent the most common defects occurring in the production phase of the chips. Test algorithms like march tests are constantly updated and validated for each new fault model. Manual validation of march tests can be very difficult due to the increasing complexity of both march tests and fault models. So, memory fault simulation is necessary to calculate fault coverage of march tests every time a new fault model is introduced. It is also used to build the fault dictionary required to perform memory diagnosis. Figure 2.11 shows the architecture of a typical memory fault simulator. It has three inputs; (a) fault List, (b) march test and (c) memory model. The result of the simulation are the coverage report and fault dictionary [11]. 21

CHAPTER 2. BACKGROUND 2.5. MEMORY TESTING Figure 2.11: Memory fault simulation [11] 22

Chapter 3 FinFET Based SRAM Design This chapter first presents the basics of conventional 6-T SRAM cell along with its design trade-offs. Then we discuss about the challenges involved in traditional MOSFET SRAM scaling and how FinFET-based SRAM helps to continue the scaling trend into sub-nanometer regime. Finally, we describe the FinFET based 6-T design by [27] and the complete electrical schematic of the SRAM model which we use to do fault modeling in Chapter 4. 3.1 SRAM Basics An SRAM cell is the key component storing a single bit of binary information. Memory circuits, mainly caches, are predicted to occupy more than 90% of the chip silicon area in the foreseeable future. This makes its design and test to be robust without any room for errors. A 6-T SRAM cell is very popular in the IC industry due to its superior robustness, low power and low voltage operation. A typical MOSFET-based 6-T SRAM cell is shown in Figure 3.1. It has two cross coupled inverters forming a latch (Q1-Q4) and two n- type access transistors (Q5 and Q6) which connects the storage node with the bit lines BL and BLB. Before every read operation, the bit lines are pre-charged to VDD by the pre-charge circuitry. The read operation is initiated by enabling the word line thereby connecting the pre charged bit lines with the internal nodes of the cell. Assume the cell stores a logic 0 in Figure 3.1. Upon read access, the bit line voltage BLB remains at the pre-charged level whereas the voltage of node BL starts to discharge through transistors Q5 and Q1. The sizing of Q1 and Q5 must ensure that inverter formed by transistors Q2 and Q4 do not switch causing a 23

CHAPTER 3. FINFET BASED SRAM DESIGN 3.1. SRAM BASICS destructive read. The cell β ratio or cell ratio (CR) is defined as: β = CR = (W 1/L1)/(W 5/L5) (3.1) Where W1 (W5), L1 (L5) represents the width and length of transistor Q1 (Q5) respectively. Typically, in order to ensure a non-destructive read and good noise margin, β ratio must be greater than one and can be varied from approximately 1 to 2.5. Increasing β ratio increases the read current (and hence the speed) and improved stability at the cost of larger cell area. A smaller β ratio ensures a more compact cell with moderate speed and stability. Once the voltage at BL discharges to a certain level compared to the precharged BLB( (BL-BLB)), the sense amplifier is enabled which amplifies the small differential voltage between the bit lines to full swing output signal. For a write operation, one of the bit lines are pulled low by the write driver such that proper sizing of the access transistor will enable the successful write of the cell. Note that the write operation is applied to the node storing a logic 1. This is necessary because of the non-destructive read constraint that ensures that a logic 0 node does not exceed the switching threshold of inverter formed by transistors Q2 and Q4. Cell pull up ratio (PR) is defined as: P R = (W 4/L4)/(W 6/L6) (3.2) Where W4 (W6), L4 (L6) represents the width and length of transistor Q4 (Q6) respectively. Pull up ratio is the ratio between sizes of the pull-up transistor to the access transistor during write operation. To minimize the cell area, the sizes of the pull-up and access transistors are chosen to be minimal and approximately the same. However, stronger access transistors and/or weaker pull-up transistors will ensure a robust write operation. For example, in Figure 3.1 to write logic 0 into the cell, BL is pulled low and BLB is at precharged state. Node T is pulled low such that it causes the output associated with inverter formed by transistors Q2 and Q4 to logic 1 thereby making node T to logic 0 resulting in a successful write. Many factors that affect the quality and cost can impose contradictory requirement on SRAM design and test. The tradeoffs in the design of SRAM cell are summarized as follows [28]: Area vs Yield : Functionality and density are the two major constraints of SRAM design. Functionality is guaranteed for large memory arrays by having higher design margins. Design margins are 24

CHAPTER 3. FINFET BASED SRAM DESIGN 3.1. SRAM BASICS Figure 3.1: Mainstream MOSFET based 6-T SRAM cell determined by device sizing, supply voltage and also by the selection of transistor threshold voltage. Although up sizing the transistors gives better noise margin, it increases the cell area and power. Read Static Noise Margin(RSNM): A read static noise margin characterizes the read stability of the SRAM cell. The RSNM is defined as the length of the side of the maximum square that can fit inside the butterfly curve (see Figure 3.2). A butterfly curve is formed by plotting the voltage transfer characteristics of the two inverters in an SRAM cell when both the bit line (BL) and word line (WL) are biased at Vdd. If the two squares inside the butterfly curve do not have equal side lengths, RSNM is defined as the side length of the smaller square. The read margin can be increased by increasing the no. of fins in the pull-down transistor, which increases the area and also write delay thereby affecting the write margin. Write Margin: Write margin is defined as the maximum BLB voltage that is able to flip the cell when BL is kept at vdd. The write margin can be increased by increasing the number of fins of the pull up transistors and access transistors at the cost of cell area and cell read margin. Access Time: During any read or write operation, the word line is raised for only a limited time called cell access time within which the cell has to be read or written. If either read or write cannot be 25

CHAPTER 3. FINFET BASED SRAM DESIGN 3.2. FINFET SRAM ADVANTAGES AND CHALLENGES Figure 3.2: Butterfly plot to measure SNM of SRAM cell [27] carried out before word line is lowered, access failure occurs. So, this means for a read operation the sufficient bit line differential voltage must be developed before the word line is lowered, so that the sense amplifier can sense reliably. Leakage Power: Even when the cell is idle, power consumption is finite due to the transistor leakage currents. Unlike the read/write margin and access time for which each cell must meet a given criterion, as far as static leakage power is concerned, designers are more interested in the total power consumption of the SRAM array. Scaling VDD will reduce total power consumption; however, the RSNM, write margin, and access time metrics will be degraded if VDD is lowered. New device architectures like FinFETs offer very good leakage power savings and are expected to replace MOSFETs in the near future. 3.2 FinFET SRAM Advantages and Challenges As memories are expected to occupy major area of future designs, scaling becomes even more challenging and important. In FinFETs the electrostatic control of a gate is improved as a result of gate control from multiple sides of the fin. Short channel effects such as subthreshold degradation, V th roll of with length and 26

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN drain induced barrier lowering (DIBL) are improved. As a FinFET s body uses very minimal doping, the threat from RDF which is considered the major hurdle in MOSFET scaling, is eliminated. Thus FinFETs can be scaled even further and Moore s law will remain active for longer time now. According to [28] there are five consequences of SRAM stability and performance because the FinFETs have the following properties: First, improved subthreshold swing that leads to lower V th for a given off-state leakage current. The on-state current per device width (W) is enhanced. For SRAM cells, the read and write access times are shortened. Second, V th rolls off less rapidly with L. As a result, V th variation is smaller for a given L variation. This leads to a lower Vdd and less power consumption. Third, in lightly doped multi-gate devices, RDF resulting from body doping becomes insignificant, further reducing V th variation. Fourth, a smaller DIBL effect leads to a smaller output conductance in the saturation region, which leads to sharper voltage transfer characteristics. This will improve the read static noise margin of SRAM cells. Finally, unlike conventional MOSFET devices, where the value of W can lie in a continuous interval, the effective width (W eff ) of multi-gate devices can have only discrete values. This might not seriously affect logic devices in which W eff is large, but it could limit the design space for circuits, such as SRAM cells, that include small devices. Given that tuning of W eff is limited, the optimization of L might be needed for SRAM cell design. 3.3 FinFET based SRAM Design In this section we give an overview of the design of FinFET-based SRAM upon which we do fault injection and analysis in the next chapter. We use the design given by [27]. The authors in [27] discuss both conventional 6-T SG (single gate) FinFET SRAM design as well as 6-T FinFET SRAM with dynamic feedback. We chose the conventional 6-T design for our analysis. We also give an overview of the 6-T 27

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN Figure 3.3: FinFET device structure [27] design with feedback in the end of this section which has its own advantages over the conventional design. All the figures and data presented in this section is taken from [27]. Since the lack of a compact device model for back gated operation of a FinFET, the authors [27] use the mixed mode device/circuit simulation using Taurus TCAD simulator [29]. Figure 3.3 shows the device structure used whereas Figure 3.4 shows the simulation parameters. A 3-D schematic view of the designed 6-T FinFET SRAM is shown in Figure 3.5 3.3.1 Fin Surface Orientation An added advantage of FinFET is that it can be easily fabricated along different channel planes in a single die. Figure 3.6 shows a silicon wafer containing differently oriented FinFET transistors. Fabrication of MOSFETs along any other plane other than (100) is difficult due to increased process variation and interface traps [30]. But with FinFETs, fabrication of transistors along (110) has become feasible, leading to design of differently oriented transistors within a circuit. Electron mobility is highest in (100) plane whereas hole mobility is highest in (110) plane. In this SRAM design, to increase the cell β ratio and to improve the cell margin, the n-type nfet pull down transistors were rotated to have channel surface along (100) plane. This 28

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN Figure 3.4: Simulation parameters [27] Figure 3.5: A 3-D schematic view of 6-T SRAM cell [27] 29

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN Figure 3.6: Silicon wafer showing different orientation of transistors [27] increases the transistor drive strength. 3.3.2 6-T SRAM Design The working principle of the FinFET 6-T design in [27] is the same as conventional MOSFETs and the schematic view and the layout of the 6-T design are shown in Figure 3.7. As seen from the layout, each transistor has one fin as its effective channel width. The cell read margin can be improved by upsizing the pull down transistors (NPD) relative to the access transistors. As illustrated in Chapter 2, FinFET s effective channel width is determined by the number of fins, so only discrete sizing is possible. Better design margins are obtained by increasing the number of fins in the NPD or by rotating the transistor s orientation. Figure 3.8 shows the layouts of the same 6-T cell with 2-fins in the NPD and rotated NPD (1-fin) respectively. The SRAM design with 2-fins in the NPD acheives 37% boost in noise margin but this comes with an area penalty. The rotated design also causes improvement in the noise margin but comes at the cost of more lithographical challenge in printing rotated fins. The results of simulations on the SRAMs are shown in Figure 3.9 which also shows the butterfly graph of the conventional MOSFET based SRAM design with cell β ratio of 1.5 and 2. As seen from the figure, 30

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN Figure 3.7: 6-T FinFET SRAM schematic and layout with 1-fin in NPD [27] the conventional SG 6-T FinFET-based SRAM with 1-fin pull-down achieves a 22% improvement in the read SNM compared to its planar MOSFET counterpart with β ratio of 1.5. By rotating the pull-down transistors as seen in section??, 15% further improvement in the read SNM, with a 13.3% area penalty, can be achieved; a 36% further improvement in the read SNM, with 16.6% area penalty, can be achieved by increasing the pull-down transistors width to 2-fins. Higher threshold pull-down devices were then used in the FinFET designs, by raising the gate work function of the nfet and pfet devices (both to 4.75eV), to reduce leakage [27]. 3.3.3 6-T SRAM Design with Dynamic Feed back Adaptive body biasing becomes less effective with Bulk-Si MOSFET scaling [31] [32]. However, back gate biasing of a FinFET transistor remains effective for dynamic control of V th with transistor scaling and Figure 3.8: 6-T SRAM layout of 2-fin NPD and rotated fin NPD [27] 31

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN Figure 3.9: Butterfly graphs of different 6-T SRAM designs [27] can provide improved control of short channel effects as well [2]. In the Independent Gate mode, the gate electrode is etched away in the region over the top of the fin. The strong back gate biasing effect can be leveraged to optimize the performance of FinFET based SRAMs. By connecting the storage nodes of SRAM cell to the back gate of the access transistors as shown in figure 3.10(a), the strength of the access transistors can be selectively and dynamically decreased. For example, consider the node that stores logic 0 as shown in the figure. It makes the back gate of the access transistor AXR to be off or in other words, it reduces its drive strength. This effectively increases the cell β ratio during the read cycle thereby increasing the read margin. There is a little increase in the cell read time incurred because of the introduced feedback. A 71% read margin improvement over the conventional SG design is achieved. Figure 3.10(b) shows the layout of this design. The main drawback of the feedback design is the reduced write margin because of the reduction in the driving current of the access transistor AXR, when it is pulled low to write a logic 0 into the cell. The authors [27] also discussed a 4-T design which increases noise margin and reduces cell area but at the cost of increased leakage power consumption compared to the 6-T designs. Figure 3.11 lists the leakage power, noise margins for all the designs discussed in this section. It highlights the benefit of 6-T design with dynamic feedback for achieving large SNM without area or leakage penalty. 32

CHAPTER 3. FINFET BASED SRAM DESIGN 3.3. FINFET BASED SRAM DESIGN Figure 3.10: FinFET 6-T SRAM design with feed back [27] Figure 3.11: Leakage, SNM of different FinFET SRAM designs [27] 33

CHAPTER 3. FINFET BASED SRAM DESIGN 3.4. FINFET SRAM ELECTRICAL SCHEMATIC 3.4 FinFET SRAM Electrical Schematic In this research, we consider a four adjacent cells of SRAM array which is the minimum required to observe the fault behavior of opens, shorts and bridge defects. Figure 3.12 shows the complete electrical schematic of FinFET-based SRAM. We have used the SG 6-T FinFET SRAM in [27] as base cell in the array. Each cell is connected to two bit lines, which are fed into a bitline multiplexer. The multiplexer selects the column by connecting the bit lines to data lines (DL and DLB) under control of the EN1 and EN2 signals. The column contains a precharge circuit, which charges the bit lines upto VDD before each operation. To write data, a write driver has been inserted. The latch based sense amplifier is designed, controlled by the Sense signal. Hspice was used to simulate the design. For Hspice simulations, we use the predictive technology model (PTM) for 20nm multi gate (MG) model [13] as well as 32nm FinFET by [33] [34]. We used the 32nm FinFET PTM to model opens on the back gate of FinFET whereas 20nm multi gate was used to model all other defect locations. This was done because 20nm muti gate model did not support independent operation of the two gates of FinFET. Supply voltage of VDD = 0.9V is used as directed by the model files. The bitline and wordline capacitances were calculated as 1pF and 1.4pF respectively to simulate the effect of having a memory array of size 1024 X 1024 (1M byte SRAM). We will briefly describe the circuit design of precharge, sense amplifer and the write driver in the following paragraphs and finally present the timing diagrams for SRAM read and write operations. Precharge Circuit: The precharge circuitry consists of three p-type FinFET transistors which are needed to charge the bitlines to VDD before each read/write operation (signal P rech ). Each transistor is designed to have channel width of 20 fins. Sense Amplifier (SA): A latch based sense amplifier is implemented in this work. This type of a SA is formed by a pair of cross-coupled inverters, much like a 6T SRAM cell. The sensing starts with biasing the latch-type SA in the high-gain metastable region by precharging and equalizing its inputs. The signal used by the precharge circuitry ( P rech ) also drives the data lines (DL and DLB) at the start of each read/write operation to equalize the inputs of sense amplifier. The signal Sense enables the SA. The n-type pull down transistors were sized to have 20 fins whereas the p-type pull up transistors were sized to have 8 fins. 34

CHAPTER 3. FINFET BASED SRAM DESIGN 3.4. FINFET SRAM ELECTRICAL SCHEMATIC Figure 3.12: FinFET-based SRAM electrical schematic 35

CHAPTER 3. FINFET BASED SRAM DESIGN 3.4. FINFET SRAM ELECTRICAL SCHEMATIC Figure 3.13: Control signal timing for a write Write Driver: The write driver is designed only as a pull down network, because the bit lines as well as the data lines are precharged to VDD before each read/write. So based on the value of input, the write driver pulls down BL or BLB. All the transistors in the write driver are sized to have 10 fins. Read and Write Time: To simplify the timing model, the switching moments of the control signals have been made the same for both write and read operations. The read time and write time of the SRAM is designed as 8ns and 6.4ns respectively. Figure 3.13 shows the control signal timing for a write logic 1 operation to cell 0. At t = 0 ns, the P rech signal is set low, and the Sense signal is set low if the previous operation is a read operation. At t = 3.0 ns, the P rech signal is set high, which ends the precharging; Write Enable is set high such that the input data is placed on the data lines; and EN1 is set high, such that BL is connected to DL, and BLB to DLB. At t = 7.0 ns, WL1, Enable and Write Enable all are set low, which ends the write operation. The control signal timing for for read is similar to that of the write but the Write Enable remains low during the complete operation, while Sense is activated at t= 5.7ns. Figure 3.14 shows the read timing signals for reading logic 0 stored in cell 0. 36

CHAPTER 3. FINFET BASED SRAM DESIGN 3.4. FINFET SRAM ELECTRICAL SCHEMATIC Figure 3.14: Control signal timing for a read 37

Chapter 4 Fault Modeling Open and short defects are responsible for significant number of failures affecting modern SRAMs. Moreover, they are becoming more common as technologies are scaled down to deep sub-micron levels where reliable fabrication is challenging. In addition, FinFETs offers a new three dimensional architecture which has to be analyzed for new fault behaviors. Based on the FinFET SRAM design discussed in Chapter 3, all possible spot defects are modeled and simulated in Hspice to observe the faulty behavior. 4.1 Introduction 4.1.1 Definition and location of opens An open defect occurs when there is a partial or total breaking of the electrical connection between two points in a circuit which should be connected by design. Figure 4.1 shows a picture of a real open in copper interconnect technology [35]. Based on the resistance, an open can be considered to be of two types: Full open: A lack of conductive material causes discontinuity which results in the complete disconnection of the two points at the defect site. Resistive open: The defect does not cause complete discontinuity but there may be very weak resistive connection between the two points. 38

CHAPTER 4. FAULT MODELING 4.1. INTRODUCTION Figure 4.1: Open defect in a metal A metal line with full open is disconnected from its driver and becomes electrically floating. This floating node may drive one (or more) transistor pair(s). The floating line voltage is determined by the following factors according to [35]: 1. Neighboring interconnect lines routed close to the floating node adds parasitic coupling capacitance to the ground or to the power plane. The value of the capacitance depends on the dielectric filling the space, distance between lines and their physical dimension. 2. If the floating node drives a transistor, then the capacitances on its source and drain determine the voltage on the node. These capacitance values depend on the transistor s operational state. 3. The third factor influencing the floating line voltage is the trapped charge accumulated in the floating structure during the fabrication process. The trapped charge is an unknown, difficult-to predict parameter. In the work by [36], measurements of the trapped charge were made on test structures consisting of floating-gate transistors with different polysilicon length extensions. These measurements always show a positive charge on the floating polysilicon, generating voltages ranging from 0.1 to 2.3 V. In case of a resistive open defect, the weak connection between two points enables electrons and holes to tunnel through, generating a slow charge transfer, which increases the rise and the fall times of the signal to be propagated through the line. Open defects in the memory cell can be classified as opens within a cell (OC), opens at bitlines (OB) and at word line (OW). All possible open defect locations of a FinFET-based SRAM is shown in Figure 4.2. Opens at locations OCx and OCxc will show a complementary fault behavior due to the symmetric 39

CHAPTER 4. FAULT MODELING 4.1. INTRODUCTION Figure 4.2: Open defects in FinFET SRAM cell structure of the memory cell as discussed in Chapter 2. So, we need to simulate OCx locations only. Their complementary faults can be easily derived. Table 4.1 describes all open fault locations (OCx). Table 4.1: List of opens [25] Name Description OC1/OC2 Source/drain of pull-up at true side broken OC3/OC4 Drain/source of pull-down at true side broken OC5 Gate of pull-up at true side broken OC6 Cross coupling at true side broken OC7 Gate of pull-down at true side broken OC8 Pass transistor connection to T broken OC9 Pass transistor connection to bit line broken OC10 Gate of pass transistor at true side broken OC11/OC12 Vcc/Vss path of the cell broken OC13 Back gate of pull-up FinFET broken OC14 Back gate of pull-down FinFET broken OC15 Back gate of access FinFET broken OBw Bit line BL broken OBr Bit line BLB broken OW The word line WL broken 4.1.2 Definition and location of shorts Shorts can occur within a cell (SC), shorts at bit lines (SB) and at word lines (SW). Shorts between Vcc and Vss are excluded, since they affect the behavior of the whole circuit not just the memory cell. Shorts at node F will show complementary behavior to shorts at node T (refer to Figure 4.2). Table 4.2 shows the possible shorts within a cell. 40

CHAPTER 4. FAULT MODELING 4.1. INTRODUCTION Table 4.2: List of shorts [25] Shorts Faulty behavior Comp. behavior SC1 T-V cc F-V cc SC2 T-V ss F-V ss SB1 BL-V cc BL-V cc SB2 BL-V ss BL-V ss SW1 WL-V cc SW1 WL-V ss 4.1.3 Definition and location of bridges A bridge in an SRAM array can connect any pair of nodes. Bridge defects can occur between nodes within a cell or between cells of the array. All bridges connecting two nodes of the same cell, including the pair of bit lines and word lines to which it is connected. Table 4.3 lists all possible bridge defects within a cell. Table 4.3: List of bridges within a cell [25] Bridge Faulty behavior Comp. behavior BC1 T-F BC2 T-BL F-BL BC3 T-BL F-BL BC4 T-WL F-WL BC5 BL-BL BC6 BL-WL BL-WL Bridge defects may also connect nodes of adjacent cells, including bit lines and word lines. The defective cells may be in the same row (denoted by rbccs) or in the same column (denoted by cbccs) or even diagonal cells (denoted by dbccs). Figure 4.3 shows a four cell configuration used by Table 4.4 to describe all possible bridge defects between adjacent cells. Table 4.4: List of bridges between adjacent cells [25] Bridge Faulty behavior Comp. behavior rbcc1 T0-T2 F0-F2 rbcc2 T0-F2 F0-T2 rbcc3 T0-BL1 F0-BLB1 rbcc4 T0-BLB1 F0-BL1 rbcc5 BL-BL1 BLB-BLB1 rbcc6 BL-BLB1 cbcc1 T0-T1 F0-F1 cbcc2 T0-F1 F0-T1 cbcc3 T0-WL2 F0-WL2 cbcc4 WL1-WL2 dbcc1 T0-T3 FO-F3 dbcc2 T0-F3 F0-T3 41

CHAPTER 4. FAULT MODELING 4.2. PRIMITIVES FOR DRIVING THE SIMULATOR Figure 4.3: Four cell configuration 4.2 Primitives for Driving the Simulator Figure 4.4 shows the block diagram of our fault modeling architecture. We consider two single SRAM cells in a column along with peripheral circuitry and lumped capacitances added as described in Chapter 3. In Figure 4.4: Fault modeling architecture 42