V DSS R DS(on) max I D

Applications l High frequency DC-DC converters Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN01) Fully Characterized Avalanche Voltage and Current l l l PD - 93804B IRFB41N15D IRFIB41N15D IRFS41N15D IRFSL41N15D HEXFET Power MOSFET V DSS R DS(on) max I D 150V 0.045: 41A TO-220AB IRFB41N15D TO-220 FullPak IRFIB41N15D D 2 Pak IRFS41N15D TO-262 IRFSL41N15D Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 41 I D @ T C = 0 C Continuous Drain Current, V GS @ V 29 A I DM Pulsed Drain Current c 164 P D @T A = 25 C Power Dissipation, D 2 Pak 3.1 W P D @T C = 25 C Power Dissipation, TO-220 200 P D @T C = 25 C Power Dissipation, Fullpak Linear Derating Factor, TO-220 48 1.3 W/ C Linear Derating Factor, Fullpak 0.32 V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt e 2.7 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for seconds Mounting torque, 6-32 or M3 screw 300 (1.6mm from case ) 1.1() N m (lbf in) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 C/W R θjc Junction-to-Case, Fullpak 3.14 R θcs Case-to-Sink, Flat, Greased Surface h 0.50 R θja Junction-to-Ambient, TO-220 h 62 R θja Junction-to-Ambient, D 2 Pak i 40 R θja Junction-to-Ambient, Fullpak 65 Notes through are on page 12 www.irf.com 1 07/16/03

Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 150 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.17 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 0.045 Ω V GS = V, I D = 25A f V GS(th) Gate Threshold Voltage 3.0 5.5 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 µa V DS = 150V, V GS = 0V 250 V DS = 120V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 na V GS = 30V Gate-to-Source Reverse Leakage -0 V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 18 S V DS = 50V, I D = 25A Q g Total Gate Charge 72 1 I D = 25A Q gs Gate-to-Source Charge 21 31 nc V DS = 120V Q gd Gate-to-Drain ("Miller") Charge 35 52 V GS = V f t d(on) Turn-On Delay Time 16 V DD = 75V t r Rise Time 63 I D = 25A t d(off) Turn-Off Delay Time 25 ns R G = 2.5Ω t f Fall Time 14 V GS = V f C iss Input Capacitance 2520 V GS = 0V C oss Output Capacitance 5 V DS = 25V C rss Reverse Transfer Capacitance 1 pf ƒ = 1.0MHz C oss Output Capacitance 3090 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 230 V GS = 0V, V DS = 120V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 250 V GS = 0V, V DS = 0V to 120V g Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 470 mj I AR Avalanche Currentc 25 A E AR Repetitive Avalanche Energy c 20 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 41 MOSFET symbol (Body Diode) A showing the I SM Pulsed Source Current 164 integral reverse G (Body Diode)c p-n junction diode. V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 25A, V GS = 0V f t rr Reverse Recovery Time 170 260 ns T J = 25 C, I F = 25A Q rr Reverse Recovery Charge 1.3 1.9 µc di/dt = 0A/µs f t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) D S 2 www.irf.com

I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 9.0V 8.0V 7.5V 7.0V 6.5V BOTTOM 6.0V I D, Drain-to-Source Current (A) 00 0 VGS TOP 15V V 9.0V 8.0V 7.5V 7.0V 6.5V BOTTOM 6.0V 6.0V 6.0V 20µs PULSE WIDTH T J = 25 C 1 0.1 1 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 175 C 1 0.1 1 0 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 00 0 T J = 175 C T = 25 J C V DS= 25V 20µs PULSE WIDTH 1 6 7 8 9 11 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 41A 2.5 2.0 1.5 1.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 120 140 160 180 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3

C, Capacitance(pF) IRFB/IRFIB/IRFS/IRFSL41N15D 0000 000 00 0 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 1 0 00 V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage V GS, Gate-to-Source Voltage (V) 20 16 12 8 4 I = D 25A V DS = 120V V DS = 75V V DS = 30V FOR TEST CIRCUIT SEE FIGURE 13 0 0 20 40 60 80 0 120 Q G, Total Gate Charge (nc) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 00 0 1 T J = 175 C T J = 25 C V GS = 0 V 0.1 0.2 0.6 1.0 1.4 1.8 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us 1ms T = 25 C ms C TJ = 175 C Single Pulse 1 1 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com

50 V DS R D I D, Drain Current (A) 40 30 20 0 25 50 75 0 125 150 175 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature Fig a. Switching Time Test Circuit V DS 90% R G V GS V GS Pulse Width 1 µs Duty Factor 0.1 % D.U.T. % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms - V DD Thermal Response (Z thjc ) 1 D = 0.50 0.20 PDM 0.1 0. t1 0.05 t2 0.02 0.01 SINGLE PULSE Notes: (THERMAL RESPONSE) 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc TC 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5

R G V DS 20V V GS tp L D.U.T IAS 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp 15V DRIVER - V DD A V (BR)DSS E AS, Single Pulse Avalanche Energy (mj) 1200 00 800 600 400 200 I D TOP 7.3A 13A BOTTOM 18A TOP BOTTOM A 21A 25A 0 25 50 75 0 125 150 175 Starting T, Junction Temperature ( J C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V GS Q GS Q GD D.U.T. V - DS V GS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6 www.irf.com

Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs www.irf.com 7

TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.3).54 (.415).29 (.405) 3.78 (.149) 3.54 (.139) - A - 4.69 (.185) 4.20 (.165) - B - 1.32 (.052) 1.22 (.048) 15.24 (.600) 14.84 (.584) 4 6.47 (.255) 6. (.240) 1 2 3 1.15 (.045) MIN LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 1.15 (.045) 3X 0.93 (.037) 0.69 (.027) 0.36 (.014) M B A M 0.55 (.022) 3X 0.46 (.018) 2.92 (.115) 2.64 (.4) 2.54 (.0) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C For GB Production EXAMPLE: THIS IS AN IRF LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" INTERNATIONAL RECTIFIER LOGO LOT CODE PART NUMBER DATE CODE 8 www.irf.com

TO-220 Full-Pak Package Outline Dimensions are shown in millimeters (inches) IRFB/IRFIB/IRFS/IRFSL41N15D 16.00 (.630) 15.80 (.622).60 (.417).40 (.409) 1 2 3 3.40 (.133) ø 3. (.123) - A - 3.70 (.145) 3.20 (.126) 1.15 (.045) MIN. 3.30 (.130) 3. (.122) 4.80 (.189) 4.60 (.181) 7. (.280) 6.70 (.263) 2.80 (.1) 2.60 (.2) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982 2 CONTROLLING DIMENSION: INCH. 13.70 (.540) 13.50 (.530) - B - C D 1.40 (.055) 3X 1.05 (.042) 2.54 (.0) 2X 0.90 (.035) 3X 0.70 (.028) 0.25 (.0) M A M B 0.48 (.019) 3X 0.44 (.017) 2.85 (.112) 2.65 (.4) A B MINIMUM CREEPAGE DISTANCE BETWEEN A-B-C-D = 4.80 (.189) TO-220 Full-Pak Part Marking Information Notes : This part marking information applies to all devices produced before 02/26/2001 and currently for parts manufactured in GB. EXAMPLE: THIS IS AN IRFI840G WITH AS S EMBLY LOT CODE E401 INTERNATIONAL RECTIFIER LOGO IRFI840G E401 9245 PART NUMBER AS S E MBL Y LOT CODE DATE CODE (YYWW) YY = YEAR WW = WEEK Notes: This part marking information applies to devices produced after 02/26/2001 in location other than GB. EXAMPLE: THIS IS AN IRFI840G WIT H AS S E MBLY LOT CODE 3432 ASSEMBLED ON WW 24 1999 IN THE ASSEMBLY LINE "K" INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE IRFI840G 924K 34 32 PART NUMBER DATE CODE YEAR 9 = 1999 WEEK 24 LINE K www.irf.com 9

D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 ASSEMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L www.irf.com

TO-262 Package Outline Dimensions are shown in millimeters (inches) IRFB/IRFIB/IRFS/IRFSL41N15D IGBT 1- GATE 2- COLLECTOR 3- EMITTER TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL33L LOT CODE 1789 ASSEMBLED ON WW 19, 1997 IN THE ASS EMBLY LINE "C" INT ERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C www.irf.com 11

D 2 Pak Tape & Reel Information TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065).90 (.429).70 (.421) 11.60 (.457) 11.40 (.449) 16. (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 1.5mH, R G = 25Ω, I AS = 25A. ƒ I SD 25A, di/dt 340A/µs, V DD V (BR)DSS, T J 175 C. Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS This is only applied to TO-220AB package. This is applied to D 2 Pak, when mounted on 1" square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. TO-220AB & TO-220 FullPak packages are not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.07/03 12 www.irf.com

Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/