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Interleaved ADCs EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 1 Summary Last Lecture Pipelined ADCs (continued) Effect gain stage, sub-dac non-idealities on overall ADC performance Digital calibration (continued) Correction for inter-stage gain nonlinearity Implementation Practical circuits Combining the digital bits Stage implementation Circuits Noise budgeting EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page

Time Interleaved Converters Example: 4 ADCs operating in parallel at sampling frequency f s Each ADC converts on one of the 4 possible clock phases Overall sampling frequency= 4f s Note T/H has to operate at 4f s! Extremely fast: Typically, limited by speed of T/H V IN 4f s T/H f s ADC f s +T s /4 ADC f s +T s /4 ADC Output Combiner Digital Output Accuracy limited by mismatch among individual ADCs (timing, offset, gain, ) f s +3T s /4 ADC EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 3 Oversampled ADCs EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 4

Analog-to-Digital Converters Two categories: Nyquist rate ADCs f sig max ~ 0.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max. 1-14bits Oversampled ADCs f sig max << 0.5xf sampling Maximum possible signal bandwidth lower compared to nyquist Maximum achievable resolution high (18 to 0bits!) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 5 The Case for Oversampling Nyquist sampling: Signal f s B Freq narrow transition AA-Filter f s >B +δ Sampler Nyquist ADC DSP Oversampling: Signal f s >> f N?? B Freq wide transition AA-Filter f s = Mf N Sampler Oversampled ADC DSP Nyquist rate f N = B Oversampling rate M = f s /f N >> 1 EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 6

Nyquist v.s. Oversampled Converters Antialiasing X(f) Input Signal f B frequency Nyquist Sampling f B f s f S ~f B Anti-aliasing Filter f s Oversampling frequency f B f S >> f B f s frequency EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 7 Oversampling Benefits No stringent requirements imposed on analog building blocks Takes advantage of the availability of low cost, low power digital filtering Relaxed transition band requirements for analog anti-aliasing filters Reduced baseband quantization noise power Allows trading speed for resolution EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 8

ADC Converters Baseband Noise For a quantizer with step size Δ and sampling rate f s : Quantization noise power distributed uniformly across Nyquist bandwidth ( f s /) N e (f) N B -f B f s / -f s / f B Power spectral density: e Δ 1 N(f) e = = fs 1 fs Noise is distributed over the Nyquist band f s / to f s / EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 9 Oversampled Converters Baseband Noise fb fb Δ 1 SB = N e( f )df = df fb fb 1 fs N e (f) Δ fb = 1 f N B s where for fb = f s/ Δ SB0 = -f s / -f B f B f s / 1 fb SB0 SB = SB0 = f s M fs where M = = oversampling ratio f B EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 10

B Oversampled Converters Baseband Noise fb SB0 SB = SB0 = f s M fs where M = = oversampling ratio f X increase in M 3dB reduction in S B ½ bit increase in resolution/octave oversampling To increase the improvement in resolution: Embed quantizer in a feedback loop Noise shaping (sigma delta modulation) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 11 Pulse-Count Modulation V in (kt) Nyquist ADC 0 1 t/t V in (kt) Oversampled ADC, M = 8 0 1 t/t Mean of pulse-count signal approximates analog input! EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 1

Pulse-Count Spectrum Magnitude f Signal: low frequencies, f < B << f s Quantization error: high frequency, B f s / Separate with low-pass filter! EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 13 Oversampled ADC Predictive Coding v IN + _ ADC D OUT 1-bit Digital Filter N-bit Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1-Bit digital output Digital filter computes average N-bit output EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 14

Oversampled ADC Signal B Freq wide transition Analog AA-Filter f s = Mf N Sampler E.g. Pulse-Count Modulator Modulator 1-Bit Digital f s1 = M f N Decimator narrow transition Digital AA-Filter N-Bit Digital f s = f N + δ DSP Decimator: Digital (low-pass) filter Removes quantization error for f > B Provides anti-alias filtering for DSP Narrow transition band, high-order 1-Bit input, N-Bit output (essentially computes average ) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 15 Modulator (AFE) Objectives: Convert analog input to 1-Bit pulse density stream Move quantization error to high frequencies f >>B Operates at high frequency f s >> f N M = 8 56 (typical).104 Since modulator operated at high frequencies need to keep circuitry simple ΣΔ = ΔΣ Modulator EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 16

Sigma- Delta Modulators Analog 1-Bit ΣΔ modulators convert a continuous time analog input v IN into a 1-Bit sequence D OUT f s V IN + _ H(z) D OUT DAC Loop filter 1b Quantizer (comparator) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 17 Sigma-Delta Modulators The loop filter H can be either switched-capacitor or continuous time Switched-capacitor filters are easier to implement + frequency characteristics scale with clock rate Continuous time filters provide anti-aliasing protection f s V IN + _ H(z) D OUT DAC EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 18

Oversampling A/D Conversion f s f s /M Input Signal Bandwidth B=f s /M Oversampling Modulator (AFE) 1-bit @ f s Decimation Filter n-bit @ f s /M f s = sampling rate M= oversampling ratio Analog front-end oversampled noise-shaping modulator Converts original signal to a 1-bit digital output at the high rate of (BXM) Digital back-end digital filter (decimation) Removes out-of-band quantization noise Provides anti-aliasing to allow re-sampling @ lower sampling rate EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 19 1 st Order ΣΔ Modulator 1 st order modulator, simplest loop filter an integrator V IN + _ H(z) = z -1 1 z -1 D OUT DAC Note: Non-linear system with memory difficult to analyze EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 0

1 st Order ΣΔ Modulator Switched-capacitor implementation V IN φ 1 φ φ - + 1,0 D OUT +Δ/ -Δ/ Full-scale input range Δ Note that Δ here is different from Nyquist rate ADC Δ (1LSB) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 1 1 st Order ΔΣ Modulator V IN -Δ/ V IN +Δ/ + _ D OUT -Δ/ or +Δ/ DAC Properties of the 1 st order modulator: Maximum analog input range is equal to the DAC reference The average value of D OUT must equal the average value of V IN +1 s (or 1 s) density in D OUT is an inherently monotonic function of V IN To 1 st order, linearity is not dependent on component matching Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page

Analog input -Δ/ V in +Δ/ 1 st Order ΣΔ Modulator Sine Wave Tally of quantization error 1 X z -1-1 1-z Integrator Q Comparator 1-Bit quantizer 3 Y 1-Bit digital output stream, -1, +1 Instantaneous quantization error Implicit 1-Bit DAC +Δ/, -Δ/ (Δ = ) M chosen to be 8 (low) to ease observability EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 3 1 st Order Modulator Signals 1.5 1 1st Order Sigma-Delta X Q Y X analog input Q tally of q-error Y digital/dac output Amplitude 0.5 0-0.5 Mean of Y approximates X That is exactly what the digital filter does -1-1.5 0 10 0 30 40 50 60 Time [ t/t ] T = 1/f s = 1/ (M f N ) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 4

ΣΔ Modulator Characteristics Inherently linear for 1-Bit DAC Quantization noise and thermal noise (KT/C) distributed over f s / to +f s / Total noise within signal bandwidth reduced by 1/M Required capacitor sizes x1/m compared to nyquist rate ADCs Very high SQNR achievable (> 0 Bits!) To first order, quantization error independent of component matching Limited to moderate & low speed EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 5 30 1 st Order ΣΔ Modulator Output Spectrum Quantization noise definitely not white! Amplitude [ dbwn ] 0 10 0-10 -0-30 -40 Input -50 0 0.1 0. 0.3 0.4 0.5 Frequency [ f /f s ] Skewed towards higher frequencies Notice the distinct tones dbwn (db White Noise) scale sets the 0dB line at the noise per bin of a random -1, +1 sequence EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 6

Quantization Noise Analysis Integrator Quantization Error e(kt) x(kt) Σ 1 z H( z) = 1 z 1 Σ Quantizer Model y(kt) Sigma-Delta modulators are nonlinear systems with memory difficult to analyze directly Representing the quantizer as an additive noise source linearizes the system EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 7 Signal Transfer Function 1 z H( z) = 1 z ω0 H( jω ) = jω 1 x(kt) Σ - Integrator H(z) y(kt) Signal transfer function low pass function: 1 HSig ( jω ) = 1 + s ω0 Y( z) H( z) 1 HSig ( z) = = = z X( z) 1 + H( z) Delay Magnitude f 0 Frequency EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 8

v i Σ - v i Σ - ω 0 jω v f n f 0 Noise Transfer Function Qualitative Analysis ω0 jω v n v o v o v eq = f f 0 eq vn v = f f 0 eq vn v Σ v i - ω0 jω v o f 0 Frequency Input referred-noise zero @ DC (s-plane) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 9 x(kt) 1 st Order ΣΔ Modulator STF and NTF Σ Quantization Error e(kt) Integrator 1 z H( z) = 1 1 z Σ Quantizer Model y(kt) Signal transfer function: Y( z) H( z) 1 STF = = = z X( z) 1 + H( z) Delay Noise transfer function: Y ( z) 1 NTF = = = 1 z E( z) 1+ H ( z) 1 Differentiator EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 30

jωt/ Noise Transfer Function Y() z 1 1 jωt NTF = = = 1 z set z = e Ez () 1 + Hz () jωt NTF( jω) = (1 e )=e = e jsin T/ jωt/ / j ( ωt ) e ( ω ) jωt/ ( ω ) jπ ( ω ) = e e sin T/ ( ωt π) / = sin / where T = 1/ fs Thus: NTF( f ) =sin T / =sin π f / f e jωt/ jωt/ e ( s ) Output noise power spectrum: N ( f) = NTF( f) N ( f) y e EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 31 First Order ΣΔ Modulator Noise Transfer Characteristics Noise Shaping Function Low-pass Digital Filter N ( f ) = NTF( f ) N ( f ) y ( π ) = 4sin f / f N ( f ) First-Order Noise Shaping s e e f B f N f s / frequency Key Point: Most of quantization noise pushed out of frequency band of interest EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 3

Quantizer Error For quantizers with many bits Δ ( kt ) = 1 Let s use the same expression for the 1-bit case Use simulation to verify validity e Experience: Often sufficiently accurate to be useful, with enough exceptions to be careful EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 33 First Order ΣΔ Modulator Simulated Noise Transfer Characteristic Amplitude [ dbwn ] 0 10 0-10 -0-30 Signal Simulated output spectrum Computed NTF ( π ) N ( f ) = 4 sin f / f y s Confirms assumption of quantization noise being white at insertion point Linearized model seems to be accurate -40 0 0.1 0. 0.3 0.4 0.5 Frequency [f /f s ] EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 34

First Order ΣΔ Modulator In-Band Quantization Noise ( ) NTF z = 1 z 1 s ( ) ( π ) NTF f = 4 sin f / f for M >> 1 Y B B Q ( ) ( ) S = S f NTF z df z= e π jft fs M fs M 1 Δ f 1 s ( sinπ ft) df S Q π 1 Δ 3 3 M 1 Total in-band quantization noise EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 35 1 st Order ΣΔ Dynamic Range full-scale signal power S X DR = 10log 10log inband noise power = SQ S S S S X Q X Q 1 Δ = sinusoidal input, STF = 1 π 1 Δ = 3 3 M 1 9 3 = M π 9 3 9 DR = 10log M = 10log + 30log M π π M DR 16 33 db 3 4 db 104 87 db DR = 3.4dB + 30log M X increase in M 9dB (1.5-Bit) increase in dynamic range EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 36

Oversampling and Noise Shaping ΣΔ modulators have interesting characteristics Unity gain for input signal V IN Significant attenuation of in-band quantization noise injected at quantizer input Performance significantly better than 1-bit noise quantizer performance possible for frequencies << f s Increase in oversampling (M = f s /f N >> 1) improves SQNR considerably 1 st order ΣΔ: DR increases 9dB for each doubling of M To first order, SQNR independent of circuit complexity and accuracy Analysis assumes that the quantizer noise is white Not entirely true in practice, especially for low-order modulators Practical modulators suffer from other noise sources also (e.g. thermal noise) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 37 1 st Order ΣΔ Modulator Response to DC Input Matlab & Simulink model used Input DC at 1/11 full-scale level 1 X Q 3 Y DC Input=1/11 FS z -1-1 1-z Integrator Comparator EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 38

1 st Order ΣΔ Response to DC Input Amplitude [ dbwn ] 0 0-0 -40 DC Component 0 0.1 0. 0.3 0.4 0.5 Frequency [ f /f s ] DC input A = 1/11 Output spectrum shows DC component plus distinct tones!! Tones frequency shaped the same as quantization noise More prominent at higher frequencies Seems like periodic quantization noise EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 39 Output 0.4 0. 0-0. -0.4 Limit Cycle Oscillation First order sigma-delta, DC input 0 10 0 30 40 50 Time [t/t] DC input 1/11 Periodic sequence: 1 +1 +1 3-1 4 +1 5-1 6 +1 7-1 8 +1 9-1 10 +1 11-1 Average =1/11 EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 40

1 st Order ΣΔ Limit Cycle Oscillation Amplitude In-band spurious tone with f ~ DC input level First-Order Noise Shaping f B f N Frequency f s / Problem: quantization noise becomes periodic in response to low level DC inputs & could fall within passband of interest! Solution: Use dithering (inject noise-like signal at the input ): randomizes quantization noise - If circuit thermal noise is large enough acts as dither Second order loop EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 41 1 st Order ΣΔ Modulator Linearized Model Analysis ( ) 1 1 Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 4

nd Order ΣΔ Modulator Two integrators in series Single quantizer (typically 1-bit) Feedback from output to both integrators Tones less prominent compared to 1st order EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 43 nd Order ΣΔ Modulator Linearized Model Analysis ( ) Recursive drivation: Y = X + E E + E n n 1 n n 1 n ( ) 1 1 1 Using the delay operator z : Y( z) = z X( z) + 1 z E( z) LPF HPF EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 44

NTF z NTF 4 1 ( ) = ( 1 z ) ( f ) = ( π ) nd Order ΣΔ Modulator In-Band Quantization Noise = sin f / f for M >> 1 B Q = Q ( ) ( ) z= e B fs fs M M 1 Δ f 1 s S S f NTF z df 4 1 Δ 5 π 5 M 1 s 4 ( sinπ ft) π jft 4 df EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 45 Quantization Noise nd Order ΣΔ Modulator vs 1 st Order Modulator S Q π 1 Δ 3 3 M 1 Noise Shaping Function Ideal Low-pass Digital Filter nd -Order Noise Shaping 1 st Order Noise Shaping S Q 4 π 1 Δ 5 5 M 1 f B Frequency f s / EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 46

4 nd Order ΣΔ Modulator Dynamic Range full-scale signal power S X DR = 10log 10log inband noise power = SQ S S S S X Q X Q 1 Δ = sinusoidal input, STF = 1 π 1 Δ = 5 5 M 1 15 5 = M 4 π 15 5 15 DR = 10log M = 10log + 50log M 4 4 π π DR = 11.1dB+ 50log M X increase in M 15dB (.5-bit) increase in DR EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 47 nd Order vs 1 st Order ΣΔ Modulator Dynamic Range M 16 nd Order D.R. 49 db (7.8bit) 1 st Order D.R. 33dB (5.bit) Resolution ( nd order - 1 st order).6 bit 3 64 db (10.3bit) 4dB (6.7bit) 3.6 bit 56 109 db (17.9bit) 68.8dB (11.1bit) 6.8 bit 104 139 db (.8bit) 87dB (14.bit) 8.6 bit Note: For higher oversampling ratios resolution of nd order modulator significantly higher compared to 1 st order EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 48

Digital audio application Signal bandwidth 0kHz Desired resolution 16-bit nd order ΣΔ nd Order ΣΔ Modulator Example 16 bit 98 db Dynamic Range DR = -11.1dB + 50log M Mmin = 153 M 56= 8 two reasons: 1. Allow some margin so that thermal noise dominate & provides dithering. Choice of M power of ease of digital filter implementation Sampling rate (x0khz + 5kHz)M = 1MHz (quite reasonable!) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 49 Limit Cycle Tones in 1 st Order & nd Order ΣΔ Modulator Higher oversampling ratio lower tones nd order tones much lower compared to 1 st 6dB 1 st Order ΣΔ Modulator Xincrease in M decreases the tones by 6dB for 1 st order loop and 1dB for nd order loop 1dB Inband Quantization noise nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 6, pp. 618-67, April 1991. R. Gray, Spectral analysis of quantization noise in a single-loop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp. 588 599, June 1989. EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 50

ΣΔ Implementation Practical Design Considerations Internal node scaling & clipping Effect of finite opamp gain & linearity KT/C noise Opamp noise Effect of comparator nonidealities Power dissipation considerations EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 51 Switched-Capacitor Implementation nd Order ΣΔ Nodes Scaled for Maximum Dynamic Range Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input full-scale (Δ) Note: Non-idealities associated with nd integrator and quantizer when referred to the ΣΔ input is attenuated by 1 st integrator high gain The only building block requiring low-noise and high accuracy is the 1 st integrator Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 5

nd Order ΣΔ Modulator Example: Switched-Capacitor Implementation V IN Dout Fully differential front-end Two bottom-plate integrators 1-bit DAC is made of switches and Vrefs EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 53 Switched-Capacitor Implementation nd Order ΣΔ Phase 1 V IN Dout During phase 1: 1 st integrator samples Vin on 1 st stage C1 nd integrator samples output of 1 st integrator Comparator senses polarity of nd intg. output result saved in output latch S3 opens prior to S1 minimize effect of charge injection EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 54

Switched-Capacitor Implementation nd Order ΣΔ Phase V IN Dout Input sampled during φ 1 transferred to C integration Note: S connects integrator inputs to + or Vref, polarity depends on whether Dout is 0 or 1 EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 55 nd Order ΣΔ Modulator Switched-Capacitor Implementation The ½ loss in front of each integrator implemented by choice of: C =C 1 f 0 intg =f s /(4π) EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 56

Design Phase Simulations Design of oversampled ADCs requires simulation of extremely long data traces SPICE type simulators: Normally used to test for gross circuit errors only Too slow for detailed performance verification Typically, behavioral modeling is used in MATLAB-like environments Circuit non-idealities either computed or found by using SPICE at subcircuit level Non-idealities introduced in the behavioral model one-by-one first to fully understand the effect of each individually Next step is to add as many of the non-idealities simultaneously as possible to verify whether there are interaction among non-idealities EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 57 nd Order ΣΔ Effect of 1 st Integrator Maximum Signal Handling Capability on SNR Behavioral model Non-idealities tested one by one M=56 1 st integrator maximum signal handling: 1.4, 1.5,1.6, and 1.7X Δ Effect of 1 st Integrator maximum signal handling capability on converter SNR No SNR loss for max. sig. handling >1.7Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec. 1988. EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 58

nd Order ΣΔ Effect of nd Integrator Maximum Signal Handling Capability on SNR nd integrator maximum signal handling: 0.75,1,1.5, 1.5, and 1.7X Δ Effect of nd Integrator maximum signal handling capability on SNR Νο SNR loss for max. sig. handling >1.7 Δ Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec. 1988. EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 59 nd Order ΣΔ Effect of Integrator Finite DC Gain V i Integrator φ 1 φ CI Cs - a + a opamp gain at DC V o H ( z) H ( z) ideal Finit DC Gain ( ) 1 Cs z = 1 CI 1 z a z Cs 1 + a + Cs = CI CI 1 + a 1 z Cs 1 + a + CI H DC = a 1 1 EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 60

log H ( s) a nd Order ΣΔ Effect of Integrator Finite DC Gain Ideal Integ. (a=infinite) ω 0 ω P1 = 0 Integrator magnitude a response e Q + _ H ( ω ) D OUT Note: Quantization transfer function wrt output has integrator in the feedback path: Dout = 1 eq 1 + H( ω) @ DC for ideal integ: Dout = 0 eq @ DC for real integ: Dout 1 e a Q EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 61 nd Order ΣΔ Effect of Integrator Finite DC Gain Max signal level a f 0 /a Low integrator DC gain Increase in total in-band quantization noise Can be shown: If a > M (oversampling ratio) Insignificant degradation in SNR Normally DC gain designed to be >> M in order to suppress nonlinearities EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 6

nd Order ΣΔ Effect of Integrator Finite DC Gain M / a Example: a =M 0.4dB degradation in SNR a =M 1.4dB degradation in SNR Ref: B.E. Boser et. al, The Design of Sigma-Delta Modulation A/D Converters, JSSC, Dec. 1988. EECS 47 Lecture 4 Oversampled ADCs 008 H.K. Page 63