Comparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits

Similar documents
CNTFET Based Energy Efficient Full Adder

Performance Optimization of Dynamic and Domino logic Carry Look Ahead Adder using CNTFET in 32nm technology

Design of low threshold Full Adder cell using CNTFET

Simulation and Analysis of CNTFETs based Logic Gates in HSPICE

Analysis of Power Gating Structure using CNFET Footer

Design and Performance Analysis of SOI and Conventional MOSFET based CMOS Inverter

IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 03, 2014 ISSN (online):

Design and Analysis of High Frame Rate Capable Active Pixel Sensor by Using CNTFET Devices for Nanoelectronics

International Journal on Emerging Technologies 6(1): 24-29(2015) ISSN No. (Print) : ISSN No. (Online) :

Design a Low Power CNTFET-Based Full Adder Using Majority Not Function

Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE

Low Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique

Experimental Design of a Ternary Full Adder using Pseudo N-type Carbon Nano tube FETs.

Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates

Leakage Power Reduction for Logic Circuits Using Variable Body Biasing Technique

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Practical Information

ISSN Vol.06,Issue.05, August-2014, Pages:

DIGITAL VLSI LAB ASSIGNMENT 1

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

A Novel Quaternary Full Adder Cell Based on Nanotechnology

Performance Evaluation of CNTFET Based Ternary Basic Gates and Half Adder

Probabilistic Modelling of Performance Parameters of Carbon Nanotube Transistors

Digital Electronics Part II - Circuits

LOW LEAKAGE CNTFET FULL ADDERS

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Sleepy Keeper Approach for Power Performance Tuning in VLSI Design

A Review Of Conventional And Emerging Power Gating Techniques For Leakage Power Reduction

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES

Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM

8. Combinational MOS Logic Circuits

A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS.

ENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Practical Information

Efficient CNFET-based Rectifiers for Nanoelectronics

Comparative Analysis of Low Power and High Performance PTM Models of CMOS with HiK-Metal Gate Technology at 22nm

Analysis of Total Voltage Source Power Dissipation in 6t Cntfet Sram and Force Stacking Cntfet Sram at Low Supply Voltage

INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010

CMOS VLSI Design (A3425)

Low Power &High Speed Domino XOR Cell

FinFET-based Design for Robust Nanoscale SRAM

Carbon Nanotube Based Circuit Designing: A Review

CMOS VLSI Design (A3425)

Figure.1. Schematic of 4-bit CLA JCHPS Special Issue 9: June Page 101

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;

Part II: The MOS Transistor Technology. J. SÉE 2004/2005

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I

Optimizing the Performance of Full adder, NAND by the Use of Parameters of Nano Tube Carbon Field Effect Transistor Technology

Today's Goals. Finish MOS transistor Finish NMOS logic Start CMOS logic

Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs)

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer

Stanford University. Virtual-Source Carbon Nanotube Field-Effect Transistors Model. Quick User Guide

Lecture #29. Moore s Law

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

Low Power, Area Efficient FinFET Circuit Design

1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)

Implementation of Mod-16 Counter using Verilog-A Model of CNTFET

Leakage Power Reduction in CMOS VLSI

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already

MOS Capacitance and Introduction to MOSFETs

45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random


Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

CNTFET Based Analog and Digital Circuit Designing: A Review

Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

Total reduction of leakage power through combined effect of Sleep stack and variable body biasing technique

2-Bit Magnitude Comparator Design Using Different Logic Styles

CHAPTER 3 NEW SLEEPY- PASS GATE

Design cycle for MEMS

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Circuit level, 32 nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier

Characterization of 6T CMOS SRAM in 65nm and 120nm Technology using Low power Techniques

CHAPTER 4 CARBON NANOTUBE TRASISTOR BASED LOW POWER ANALOG ELECTRONIC CIRCUITS REALIZATION

CNTFET based Highly Durable Radix-4 Multiplier using an Efficient Hybrid Adder

DESIGN & OPTIMIZATION OF FINFET BASED DOMINO LOGIC CIRCUIT Akshay Angaria 1 *, Umesh Dutta 2, Sneha Arora 3 1,3

Variable Body Biasing Technique to Reduce Leakage Current in 4x4 DRAM in VLSI

Session 10: Solid State Physics MOSFET

problem grade total

Analysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.

LEAKAGE POWER REDUCTION TECHNIQUES FOR LOW POWER VLSI DESIGN: A REVIEW PAPER

Design of Low Power Baugh Wooley Multiplier Using CNTFET

Strain Engineering for Future CMOS Technologies

Design and Optimization Low Power Adder using GDI Technique

Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction

Performance of Near-Ballistic Limit Carbon Nano Transistor (CNT) Circuits

IMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS

A Low Power and Linear Voltage Controlled Oscillator Using Hybrid CMOS-CNFET Technology

Robust Subthreshold Circuit Designing Using Sub-threshold Source Coupled Logic (STSCL)

Domino CMOS Implementation of Power Optimized and High Performance CLA adder

RELIABILITY ANALYSIS OF DYNAMIC LOGIC CIRCUITS UNDER TRANSISTOR AGING EFFECTS IN NANOTECHNOLOGY

Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits using Modified Sleepy Keeper

Transcription:

Comparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits Saravana Maruthamuthu, Wireless Group Infineon Technologies India Private Limited, MOS-AK/GSA Workshop, December 8th 2010, San Francisco (CA)

Outline Domino logic 32nm Predictive Technology Model (PTM) based AND, OR gate cells are compared with MOSFET-like Carbon Nano-FET (CNFET) model based AND, OR gate cells The analysis done at 25 o C and 110 o C in HSPICE. Static Power, Dynamic Power and Delay measurements are done Set date Copyright Infineon Technologies 2010. All rights reserved. Page 2

Predictive Technology Model (PTM) Low Power 32nm Metal Gate / High-K / Strained-Si NMOS Characteristics of BSIM 4.0 Level 54 Nominal Predictive Technology Model Generated using the online tool of Arizona State University L eff 12.6nm V th 0.16V V dd 0.9V T ox 1nm R dsw 150 Ohm Set date Copyright Infineon Technologies 2010. All rights reserved. Page 3

Stanford Single Walled-CNFET MOSFET-like HSPICE Compact Model Characteristics CNFET drain current vs. drain-to-source voltage (V DS ) with 0.9V V GS and substrate (back gate) grounded Schematic and model parameters of CNFET compact model Set date Copyright Infineon Technologies 2010. All rights reserved. Page 4

Stanford Single Walled-CNFET MOSFET-like HSPICE Compact Model Characteristics CNFET drain current vs. drain-to-gate voltage (V GS ) with 0.9V V DS and substrate (back gate) grounded Set date Copyright Infineon Technologies 2010. All rights reserved. Page 5

Domino Gates: AND, OR Domino AND Gate Domino OR Gate V DD = 0.9V for both CNFET and 32nm CMOS Load Capacitance = 0.0002pF Set date Copyright Infineon Technologies 2010. All rights reserved. Page 6

32nm CMOS and CNFET Transistor Dimensions 32nm CMOS PTM Dimensions for Domino AND, OR Gates Transistor M1 80 M2 32 M3 80 M4 40 M5 40 M6 40 M7 40 Channel Width (w) x 10-9 m CNFET Dimensions for Domino AND, OR Gates CNFET Gate Width (Wg) x 10-9 m Chirality Vector of CNT (m,n) M1 40 (16,0) 1 M2 32 (16,0) 1 M3 40 (16,0) 1 M4 50 (19,0) 2 M5 50 (19,0) 2 M6 50 (19,0) 2 M7 50 (19,0) 2 CNT Count Channel Length = 32nm V DD = 0.9V Gate Length (Lg) = 20nm V DD = 0.9V Set date Copyright Infineon Technologies 2010. All rights reserved. Page 7

Simulation Results Static Power Measurement through DC Analysis Domino Gate Type Static Power at 25 o C in Pico watt Static power at 110 o C in Pico watt 32nm PTM CMOS AND 9065 17962 CNFET AND 80.47 348 32nm PTM CMOS OR 9214 18516 CNFET OR 92.70 578.60 Set date Copyright Infineon Technologies 2010. All rights reserved. Page 8

x 10-7 watt Simulation Results Dynamic Power of Domino AND Gate During Transient Analysis Temp = 25 o C Temp = 110 o C Set date Copyright Infineon Technologies 2010. All rights reserved. Page 9

Delay in Pico Second Simulation Results Delay Measurement using Transient Analysis for Domino AND Gate Temp = 25 o C Temp = 110 o C Set date Copyright Infineon Technologies 2010. All rights reserved. Page 10

x 10-7 watt Simulation Results Dynamic Power of Domino OR Gate During Transient Analysis Temp = 25 o C Temp = 110 o C Set date Copyright Infineon Technologies 2010. All rights reserved. Page 11

Delay in Pico Second Simulation Results Delay Measurement using Transient Analysis for Domino OR Gate Temp = 25 o C Temp = 110 o C Set date Copyright Infineon Technologies 2010. All rights reserved. Page 12

Conclusion On comparison at 25 o C and 110 o C, the CNFET domino OR gate consumes nearly 100% less static power than CMOS Domino OR gate. Transient power of CNFET domino OR is nearly 43% lesser than its CMOS counterpart. Delay of CNFET Domino OR is 40% lesser than that of CMOS gate. In case of Domino AND, CNFET AND gate offers reduction in static power by 99% and transient power of CNFET Domino AND is nearly 40% lesser than that of 32nm CMOS Domino AND gate. In terms of delay, CNFET AND gate is 36% faster than CMOS gate. The overall static and dynamic power consumption of the gate is higher at 110 o C. Set date Copyright Infineon Technologies 2010. All rights reserved. Page 13

References [1] Neil H.E Weste, David Harris, Ayan Banerjee, CMOS VLSI DESIGN Third edition, Pearson Education 2006. [2] M. Saravana, "Ultra Low Power Dual-Gate 6T and 8T Stack Forced CNFET SRAM Cells, MOS-AK workshop Rome, April 2010. http://www.mos-ak.org/rome/posters.php [3] Stanford University CNFET HSPICE Model website http://nano.stanford.edu/model.php?id=23. [4] PTM High Performance 16nm Metal Gate / High-K /Model, Nanoscale Integration and Modeling (NIMO) Group, Arizona State University, http://www.eas.asu.edu/~ptm/ [5] Jie Deng Device Modeling and Circuit Performance Evaluation For Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors, Stanford University, pp. 2-89, Jun. 2007. Set date Copyright Infineon Technologies 2010. All rights reserved. Page 14

Discussion Set date Copyright Infineon Technologies 2010. All rights reserved. Page 15

2024 © hobbydocbox.com Privacy Policy | Terms of Service | Feedback