Rapid Prototyping Tape Stencils for the Application of Solder Paste

Rapid Prototyping Tape Stencils for the Application of Solder Paste Mimi X. Yang, Karen Dowling, Debbie Senesky, H.-S. Philip Wong Stanford University 450 Serra Mall Stanford, CA 94305 Ph: 650-723-2300 Email: mxy@stanford.edu Abstract This works describes a promising method for rapid prototyping tape stencils for the application of solder paste. This process is appropriate for research settings requiring developmental flexibility and the ability to deal with small device dies. This work compares the volume of solder paste deposited versus aperture volume for several common tape materials and several common printed circuit board (PCB) stencil materials. The solder deposits are then reflowed to identify which aperture and solder paste parameters can generate successful solder bumps. Electrically conductive solder bonds for small bond pads (100 µm and larger) are demonstrated between silicon device dies and glass dies using this process. Key words flip chip bonding, laser cutting, rapid prototyping, solder paste, stencil I. Introduction Flip chip bonding (FCB) is essential in the system level integration of sensor arrays (e.g. imaging chips and ultrasonic transducers [1]) and allows for more robust packaging than traditional wire bonding [2]. It allows packaging of MEMS, microfluidics, and solid state devices into a form factor more readily usable in commercial products. While this technology is mature in industry and many methods exist to perform FCB, developing the infrastructure to create the bonds at an academic research level can be time consuming and expensive. This problem is exacerbated by the low volume processing and dynamic nature of research. The typical flip chip bonding process involves selective placement of solder paste, plated metal (e.g. electroplated, sputtered), or solder spheres on metal bond pads [3], [4]. Use of solder spheres require individual placement of spheres on pads dispersed throughout the design. The solder spheres are available in various sizes, so the correct sphere size must be selected for a specific design and application. The sphere placement service and other sophisticated techniques are commercially available, but the time commitment and non-recurring engineering cost may not be appropriate for a research setting. Plating metal to create solder bumps requires additional lithography process steps to pattern photoresist to define electroplated or evaporated metal. In contrast, use of solder paste allows for a quick and single step application of bonding material to devices with many bond pads at once [4]. The technical difficulty in the use of solder paste comes from the design of the stencil to localize paste placement. Stencils are typically thin metal sheets with apertures allowing for paste deposition. The interface tension between the solder paste on the aperture side walls versus that of the substrate determines the paste release process and hence the quality of the solder deposits and subsequent reflowed bonds. There are commonly used rules of thumb to ensure high quality and repeatable paste deposits, but the use of small bond pads require expensive thin stencils with small apertures and corresponding expensive solder paste with solder spheres small enough to fill the apertures [5]. Thus, while this process allows for developmental flexibility, the stencil cost and technique needed to align the small aperture stencil with a small device die can be daunting. The process developed here involves machining a tape stencil (laser cut by an Epilogue CO 2 laser), aligning the stencil (via a Finetech bonder), applying solder paste via a squeegee, removing the tape by careful peeling, and flipping the chip onto a substrate using the Finetech and reflowing the solder using heat (Fig. 1). Using tape rather than metal stencils allows for cheap and fast prototyping without a need for a fixture to stabilize the stencil during solder paste application. The availability of minimal thickness tape satisfies aperture design rules to enable small solder deposits for small bond pads. In addition, the adhesive of the tape permits a one-time stencil-die alignment step that gives a 1

secure stencil placement for well-placed deposits. Furthermore, the conformal adherence of the stencil limits excess paste smearing under the stencil that may be a result of high squeegee pressure [3]. Figure 1. Diagram of complete solder application process for flip chip bonding. a) Start with a silicon device die with metal pads. b) Use the flip chip bonder to align the contact side of the die with the adhesive side of the tape stencil. c) Squeegee solder paste and d) remove the stencil. e) The flip chip bonder can now be used to align and f) reflow another chip or substrate to the original device die. This work presents a comparison of solder bump quality using laser cut tapes as stencils to standardized Kapton, stainless steel, and Mylar stencils. We first determined laser cutting parameters for each type of tape for square apertures with sides measuring between 50 and 500 µm. We then characterized the solder paste deposition process by observing solder deposit volumes with respect to aperture opening volumes. Solder pastes with different sized solder spheres are used (Type III, IV, and V) to determine whether larger spheres, which are less expensive, can be used with the tape stencils to create reliable bonds between small pads. II. Methods A. Materials In designing a solder paste stencil, it is critical to consider the aspect and area ratios of the stencil apertures. The ratios predict which designs allow for consistent paste release; we wish for the paste to prefer to transfer to the device pads rather than remain attached to aperture side walls [6]. For the square apertures examined in this work, a stencil thickness of less than 1.5 mils was suggested to ensure paste release for the smallest features. Thus, the stencil materials selected in this work have thicknesses that venture to satisfy the aspect and area ratio design suggestions. While our strategy of using tape as a stencil has been previously used [7], our method focuses on using thinner films for stencils to machine smaller apertures. The most common stencil materials that are commercially available include Mylar film, Kapton film, and stainless steel. We used Mylar and Kapton films in the inhouse laser patterning and solder paste application processes as reference stencils. A stainless steel stencil was patterned by PCB & Stencils Unlimited as another reference stencil. Kapton tape, blue dicing tape, and yellow dot labels are common materials available in a laboratory setting and are selected to be patterned into tape stencils. While the actual film material may be thin, the addition of adhesive increases the overall thickness of the tape material. The specific thicknesses of each stencil material are summarized in Table 1. All stencil materials purchased for patterning are available at CS Hyde. The solder pastes used in this work are Chipquik SAC305 no-clean solder pastes. We used Type III, IV, and V solder pastes with the same flux formulation and percent metal compound. While solder pastes with smaller particle sizes exist, they are not readily purchasable for most people. B. Laser Cutting Optimization Laser parameters for the CO 2 laser of the Epilog Fusion M2 were tuned for each material to realize the smallest possible features. Smaller and regular features are achievable with a higher dpi printing property, so laser settings were maximized to the 1200 dpi setting. Laser power, speed, and frequency were iterated to achieve the smallest and most uniform horizontal and vertical cutting linewidths. For the laser system used in this work, horizontal cut linewidths are smaller than that of vertical cuts given the same laser settings. Hence, patterning quality was limited by the characteristics of the horizontal features. While the linewidth mismatch cannot be avoided in a laser cutting run limited to a single laser setting, the optimized settings were selected for the smallest linewidths and minimal mismatch between horizontal and vertical linewidths. 2

Table I. Stencil materials with corresponding laser patterning parameters and minimum feature sizes. Material Overall Thickness (mils) Epilogue Laser Settings (%) (speed, power, frequency) Horizontal Linewidth (µm) Vertical Linewidth (µm) Blue Dicing Tape 3 5,2,100 132.5383 115.8733 Yellow Dot Tape 4 2,1,50 121.6343 96.6509 Kapton Tape 2.5 4, 3, 100 64.0052 68.0450 Kapton Film 1 4, 2, 100 52.7798 70.7552 Mylar Film 1 4, 1, 100 176.0866 122.7091 Stainless Steel Stencil 2 * 0* 0* * manufactured by PCB & Stencils Unlimited Adherence to these design rules minimizes the occurrence of incomplete apertures. C. Solder Paste Application In this work, solder deposits were analyzed on blank silicon pieces uniformly sputtered with 10 nm of Ti and 160 nm of Copper. This eliminates the difficult task of stencil alignment to device features. Each stencil had all apertures of interest, and all solder deposits were printed together. All stencils were positioned flush against a silicon substrate, attached by the stencil adhesive or by a piece of tape. We then applied a thick layer of solder paste to the stencil and used a razor blade to squeegee away excess material to deposit paste in the apertures. The stencil was removed by peeling from one side of the sample to the other, within a range of 3-10 seconds, with gentle force, parallel to the square features. Excluding the stainless steel stencil, a new stencil (tape or film) was laser cut for each solder paste application. This ensured no residual stencil damage from previous solder applications. The solder was reflowed following temperature guidelines based on the Chipquik SAC 305 datasheet. The temperature curve included 60 seconds of preheat at 200 C, 30 seconds of reflow at 250 C and 3 C/second ramps. D. Optical Quantification All dimensional measurements were conducted using a non-contact Keyence 3D Laser Scanning Microscope. The Keyence Multi-file Analysis Application was used to measure solder paste deposit volumes and to analyze reflowed solder balls. E. Full Process Flow with Integrated Circuit Dies Integration of tape stencils in a packaging process flow is straightforward through the use of a flip chip bonder. Typically, the bonder is used to align and bond an integrated circuit chip to a package or board substrate. In this work, the flip chip bonder was first used to align and unite an integrated circuit chip with the tape stencil (Fig. 1). The adhesive of the stencil prevented further stencil movement and misalignment, allowing the device chip to be prepared for solder paste application. After the procedures detailed in part c, the chip was immediately flip chip bonded or heated to generate solder bumps for subsequent bonding to packaging and board substrates. III. Results A. Stencil Laser Patterning Parameters Optimal stencil patterning parameters are shown in Table 1. From this data, we determined the minimum features that were printable and the required pitch between features. Furthermore, to minimize differences between stencil output and desired design, the design figures can be adjusted by laser cut linewidths. Square apertures of sides measuring 500 µm, 300 µm, 200 µm, 100 µm, and 50µm were patterned into each stencil. For each aperture size, 5 x 5 arrays of openings were positioned with a set edge to edge distance between apertures. Arrays with edge to edge distances of 500 µm, 250 µm, and 50 µm were patterned for each aperture size and stencil material. As expected, the aperture arrays with 50 µm spacing were resolved for only the stainless steel stencil due to the large, in-house, lasing linewidths. The dimensions of the features on the stainless steel stencil matched within 10 µm of that designed. 3

Figure 2. Relative volume of solder paste deposited for each aperture size. The volume is relative to the actual aperture volume, including enlargement due to laser linewidth mismatch between actual and predicted volumes, as expected when examining the aspect and area ratios. B. Solder Paste Deposition All stencils experienced some warping during the In Fig. 2, the measured solder paste volumes are patterning procedure. For the non-tape materials, the normalized to the actual aperture volume, including opening warping can make it difficult to lay the stencil flat against the augmentation due to laser linewidths. While all pad, pitch, device die, which led to flux and solder paste leakage under and solder type configurations produced solder deposits, any the stencils. For the Mylar stencil, paste smearing under the combination that did not produce distinct and non-shorted stencil during the squeegee process was particularly deposits were not included in the figure. As seen in Fig. 2, troublesome and prevented deposition of clean and discrete the tape stencils printed solder deposits closer in volume to deposits with the large apertures. For many of these solder the actual aperture volumes. The small apertures had a larger deposits, there was excess flux between adjacent deposits. The adhesive of the tape stencils restricted paste placement; 4

solder balls were limited to aperture openings and deposits were surrounded by a ring of flux without bridging to adjacent deposits. This warping may have contributed to the trend of increased excess of deposited solder for larger apertures. In particular, the difficulty of maintaining a conformal state for the film stencils, especially during multiple squeegee passes, may have significantly promoted surplus paste deposition. Excess flux under stencils artificially increased aperture volumes during the application process by further lifting the stencil away from the silicon substrate. Future experiments may limit solder application to a single aperture at a time. However, tape stencils will still maintain the advantage of securing the stencil in place during the squeegee event. In addition, engaging with only a single aperture at a time is not representative of a true processing step in which solder paste is patterned with a stencil with various sized apertures arranged non-uniformly. C. Reflowed Solder The solder deposits were reflowed by using the main heating plate of the Finetech Flip Chip Bonder to heat each silicon substrate piece. Solder deposits require sufficient particle count and flux content to successfully reflow into a solder bump or bond. Hence, this experiment reaffirmed which solder deposits are too small, for a given paste type, to reflow consistently. Fig. 3 shows laser images of various solder deposits before and after reflow. The bumpy surface of the pre-reflow deposits are indicative of discrete solder particles. The reflowed deposits have a distinctly rounded profile and a smoother surface topography. Laser optical images were used to verify which solder paste deposits, for each stencil and solder type, successfully reflowed. Figure 3. 3D laser scanned optical images of solder deposits before and after reflow for different stencil materials. (a) Stainless steel stencil deposits before and (b) after reflow. (c) Kapton tape stencil deposits before and (d) after reflow. (e) Kapton film stencil deposits before and (f) after reflow. 5

Table II. Summary of successful paste reflows with respect to stencil type (S = Stainless Steel, Y = Yellow Dot Tape, B = Blue Dicing Tape, M = Mylar Film, KT = Kapton Tape, KF = Kapton Film) Aperture Size (Edge Length) Solder Paste Type 500 µm 300 µm 200 µm 100 µm 50 µm III Y B KT S Y B M KT KF S Y B M KT KF M KT KF No Reflow IV Y B KT S Y B M KT KF S Y B M KT KF Y B M KT KF No Reflow V Y B KT KF S Y B M KT KF S Y B M KT KF B M KT No Reflow Table II summarizes which pad sizes and solder paste combinations allowed for consistent, successful reflowed solder bumps. The smallest aperture size of 50 µm did not deposit enough solder material for any of the studied stencil materials for reflowed bumps. On the other extreme, some of the film stencil materials were not effectual in producing solder bumps from deposits of large apertures. In these scenarios, the paste smearing and leakage caused shorting between deposits and subsequent reflows, which is highly undesirable when integrating a solder paste step in a full device process flow. Depending on the pitch of the desired device solder bumping, having excess solder paste deposited may be acceptable. In this scenario, ease of stencil handling and the repeatability of reflowing solder paste into bumps may trump how well matched the deposit volume compares to the aperture volume. D. Flip Chip Bonding Demonstration We demonstrated this solder paste patterning process by flip chip bonding a 1 cm x1 cm silicon die to a 2 cm x 2 cm glass substrate (Fig. 4). These test vehicles were patterned with 10 nm of Ti and 150 nm of evaporated Ni and a liftoff procedure. The solder paste was applied to the smaller silicon die using the previously mentioned tape stencil process using blue wafer dicing tape. To electrically evaluate the solder connection, daisy chains and Kelvin structures were used as test structures on the die. Both structures were designed so that the glass substrate hosts metal leads that connect to resistor traces alternating on the glass and silicon substrates. Hence, for the current to pass through a daisy chain or Kelvin structure, a solder joint must complete the electrical connection between two adjacent daisy chain resistors (Fig. 4). Successful and consistent electrical connections were measured for solder connections between devices pads of 100 µm and larger. Exact resistance values depend on solder paste material and pad materials and must be optimized for specific devices and applications. Figure 4. Alternating daisy chain structures on silicon and glass substrates electrically connected by solder joints. Probe pads are patterned on the glass substrate, and the device is oriented so that the silicon die features and solder bumps are visible through the backside of the transparent glass substrate. IV. Conclusion From the experimental results, we have found this process to be a promising method for rapid prototyping of systems in the academic environment and could be leveraged in academic makerspaces and rapid prototyping research facilities. This process is ideal for packaging with small device dies (< 1 cm) with small features (100 µm), as commonly used in research development. Further experiments can be conducted to provide precise release and squeegee models comparable to those that have been conducted for stainless steel stencils. Regardless, the ease of the handling and application of the tape stencils make them useful tools in the laboratory Commercial stencil companies have more sophisticated and better tuned instruments to pattern stencils from Mylar, Kapton, and stainless steel. While the mismatch between designed and actual stencil aperture sizes can be minimized, the difficulties of alignment and stencil situation are not eliminated. Furthermore, while the tape stencils allow for small solder deposits, the reflow process and construction of successful solder bumps may still be limited by the availability of appropriate solder paste. Interesting extensions of this work may include analyzing tape stencils patterned by commercial stencil companies. 6

Acknowledgment Work was performed in part in the nano@stanford labs, which are supported by the National Science Foundation as part of the National Nanotechnology Coordinated Infrastructure under award ECCS-1542152. We thank Dr. J Provine, Dr. Astrid Tomada, Dr. Usha Raghuram, and Dr. Ted C. Berg from Stanford University for their insight and expertise that greatly assisted the research. References [1] A. Moini, A. Nikoozadeh, J. W. Choe, B. T. Khuri-Yakub, C. Chang, D. Stephens, L. S. Smith, and D. Sahn. "Fabrication, packaging, and catheter assembly of 2D CMUT arrays for endoscopic ultrasound and cardiac imaging." In ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels, American Society of Mechanical Engineers, 2015. pp. V003T07A008-V003T07A008. [2] S. Seal, M. D. Glover, A. K. Wallace, and H. Mantooth A. Flip-chip bonded silicon carbide MOSFETs as a low parasitic alternative to wire-bonding. In Wide Bandgap Power Devices and Applications (WiPDA), 2016 IEEE 4th Workshop on IEEE. 2016, November, pp.194-199 [3] "The Nordic Electronics Packaging Guideline", Microelectronics International, Vol. 17, 2000. [4] G. Rodriguez and D.F. Baldwin, Analysis of solder paste release in fine pitch stencil printing process, ASME Journal of Electronic Packaging, vol. 121 No. 3, 1999, pp. 169 78. [5] D. Manessis, R. Patzelt, A. Ostmann, A. Aschenbrenner, and H. Reichl, Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping. Microelectronics reliability, vol. 44 no 5, 2004, pp. 797-803. [6] QualiEco Circuits Ltd (accessed 2017, June 7) 2012 [Online] Available: http://www.qualiecocircuits.co.nz/stencil-technologyother-aspects.htm [7] B. Wettermann. (accessed 2017, June 7) 2015 [Online] Available: http://www.solder.net/images/adhesive-backed-mylar-stencils-vs- Mini-Metal-Stencils-1.pdf 7