Design and Modeling of Through-Silicon Vias for 3D Integration

Design and Modeling of Through-Silicon Vias for 3D Integration Ivan Ndip, Brian Curran, Gerhard Fotheringham, Jurgen Wolf, Stephan Guttowski, Herbert Reichl Fraunhofer IZM & BeCAP @ TU Berlin IEEE Workshop on Future Directions in IC and Package Design (FDIP) EPEP 2008, San Jose, CA 26 th October 2008 1

Outline Motivation Quantification of Some EMR Problems caused by TSVs Methods for Enhancing RF Performance of TSVs in Low Resistivity Silicon On-going Activities to Overcome TSV Design & Fabrication Challenges 2

Outline Motivation Quantification of Some EMR Problems caused by TSVs Methods for Enhancing RF Performance of TSVs in Low Resistivity Silicon On-going Activities to Overcome TSV Design & Fabrication Challenges 3

Motivation 1/2 To meet consumer demands for miniaturized, high-performance and lowcost products, 3D chip-stacked packages are needed. TSVs offer many advantages over conventional bonding techniques in facilitating 3D integration. A range of applications are emerging in which TSVs will be implemented to develop stacked and miniaturized electronic systems. 4

Motivation 2/2 Example of Application: 60 GHz Antenna Module for WLAN Applications based on Wafer Level Packaging Metal Patch Glass support for handling Top part of Through silicon vias antenna module Electrical interconnect and horizontal shielding Solder bump for interconnection to substrate 50 feeding point Metal layer (patch ground) for vertical shielding Bottom part of antenna module Source: 3DASSM Consortium 5

Outline Motivation Quantification of Some EMR Problems caused by TSVs Methods for Enhancing RF Performance of TSVs in Low Resistivity Silicon On-going Activities to Overcome TSV Design & Fabrication Challenges 6

Typical EMR Problems Associated with TSVs Electromagnetic Reliability (EMR) Problems due to Lossy Nature of Silicon At microwave frequencies, lossy nature of Si leads to severe signal attenuation and other signal/power integrity issues as well as EMI problems. S 7

Si Conductivity from which Si Losses Dominate Conductor Losses 1/4 Geometrical and Material Parameters Considered TSV diameter = separation distance between signal TSV and ground TSV = 40 µm; Er = 11.9, bulk conductivity = VARIABLE Used Analytical Approximations and 3D full-wave Simulations Silicon substrate Return-current TSV Signal TSV 3D model of signal and return-current TSVs 8

Si Conductivity from which Si Losses Dominate Conductor Losses 2/4 Using Analytical Approximations Signal & return-current TSVs can be approximated as 2 conductor TML Signal TSV d Return-current TSV Per-unit length parameters are given as R ' C ' R a u s 2 L ' ln d / 2 a ( d / 2 a) 1 d a d a 2 ln / 2 ( / 2 ) 1 G ' ( R ' jl ')( G ' jc ') 2 ln / 2 ( / 2 ) 1 d a d a By setting G=0 & neglecting losses due to radiation & proximity effect, signal attenuation due to conductor & dielectric may be approximately considered separately. 9

Si Conductivity from which Si Losses Dominate Conductor Losses 3/4 Using Analytical Approximations Signal & return-current TSVs can be approximated as 2 conductor TML 0.1 Attenuation @ 20 GHz 0.1 Attenuation @ 60 GHz Attenuation (db/um) 0.01 0.001 0.0001 Attenuation (db/um) 0.01 0.001 0.0001 0.00001 0.001 0.01 0.1 1 10 100 Bulk Conductivity (S/m) 0.00001 0.001 0.01 0.1 1 10 100 Bulk Conductivity (S/m) 0.12 S/m predicted corner conductivity 0.25 S/m predicted corner conductivity TSV attenuation Attenuation due to Si Attenuation due to conductor 10

Si Conductivity from which Si Losses Dominate Conductor Losses 4/4 Using Full-wave Simulations 0 Transmission Coefficient vs. Conductivity -1 Transmission Coefficient, S12-2 -3-4 -5-6 leveling off in the S-parameters 5 GHz 300 MHz 60 GHz 77 GHz -7-8 0.00001-5,0 0.0001-4,0 0.001-3,0 0.01-2,0-1,0 0.1 0,0 1 10 1,0 100 2,0 Bulk Conductivity (S/m) The Insertion loss obtained using full-wave simulations shows same effect as predicted with analytical approximations 11

Impact of Resistivity on RF Performance of TSVs 1/2 Intensity of EMR Problems caused by TSVs depends on Si Resistivity Approximate range obtained from vendors Low Resistivity Silicon (LRS) = > 100 S/m, (< 1 Ohm cm) Medium Resistivity Silicon (MRS) = 5 10 S/m, (10 20 Ohm cm) High Resistivity Silicon (HRS) = < 5 S/m, (> 20 Ohm cm) LRS is far more cheaper than MRS & HRS Values considered LRS = 100 S/m MRS = 10 S/m HRS = 0.2 S/m 12

Impact of Resistivity on RF Performance of Unshielded TSVs 2/2 Geometrical Parameters Considered TSV diameter = separation distance between signal TSV and ground TSV = 40 µm; TSV length =200 µm Insertion Loss considered as example Ansoft Corporation 0.00 XY Plot 1 0.2 S/m HFSSDesign2 Transmission Coefficient, S12 (db) -1.00-2.00-3.00-4.00 100 S/m 10 S/m -5.00-6.00 0.00 10.00 20.00 30.00 40.00 Freq [GHz] 50.00 60.00 70.00 80.00 Challenge: To use LRS (which is far more cheaper than MRS & HRS, but extremely lossy) to design high performance silicon-based system modules 13

Cross-talk in TSVs Ansoft Corporation -0.50-0.60-0.70 XY Plot 1 5 S/m 10 S/m HFSSDesign1 Ansoft Corporation -10.00-15.00 XY Plot 2 HFSSDesign1 Transmission Coefficient, S12 (db) -0.80-0.90-1.00-1.10-1.20-1.30-1.40-1.50 Near End Cross-talk, S13 (db) -20.00-25.00-30.00-35.00 5 S/m 10 S/m -1.60 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 Freq [GHz] -40.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 Freq [GHz] Decrease in the conductivity of the silicon results in: A nearly 50% decrease in the losses BUT, nearly no change in the cross-talk TSV Cross-talk continues to be a problem, even when losses are manageable. R S G G 14

Outline Motivation Quantification of Some EMR Problems caused by TSVs Methods for Enhancing RF Performance of TSVs in Low Resistivity Silicon On-going Activities to Overcome TSV Design & Fabrication Challenges 15

Enhancing RF Performance of TSV in Low Resistivity Silicon 1/4 Concept of Coax-TSVs P t 1 2 s S.ds S EH E H Coax-TSV 3D model of Coax TSV H-field intensity in Si around Coax-TSV from 10MHz to 1 GHz 16

Enhancing RF Performance of TSV in Low Resistivity Silicon 2/4 Coax-TSV (Si-filled) Vs Coax-TSV (Mixed-filled) Coax-TSV (Si-filled): If Si is used as dielectric, there will be no improvement in RF performance Coax-TSV (Mixed-filled): RF Performance is greatly enhanced if Si is partly replaced by low-loss dielectric e.g., BCB Coax-TSV (Si-filled) Ansoft Corporation 0.00 XY Plot 1 One_Via S/P Si Si Reference Coax-TSV (Mixed-filled) Si S/P Transmission Coefficient, S12 (db) -1.00-2.00-3.00-4.00-5.00-6.00-7.00 Coax-TSV (Mixed-filled) Coax-TSV (Si-filled) BCB Si -8.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 Freq [GHz] 17

Enhancing RF Performance of TSV in Low Resistivity Silicon 3/4 Coax-TSV (Mixed-filled) Enhancement of RF performance depends on ratio of Silicon to BCB 3 different ratios were examined. Ansoft Corporation 0.00 XY Plot 2 2.5 m 15 m One_Via 2.5 m -0.05 Coax-TSV (Mixed-filled) Si S/P BCB Si Transmission Coefficient, S12 (db) -0.10-0.15-0.20-0.25-0.30-0.35 10 m 5 m 10 m 5 m 10 m 5 m -0.40-0.45 0.00 10.00 20.00 30.00 40.00 Freq [GHz] 50.00 60.00 70.00 80.00 18

Enhancing RF Performance of TSV in Low Resistivity Silicon 4/4 Coax-TSV (Low-loss dielectric-filled) Coax-TSV (Low-loss dielectric-filled) Coax-TSV (Lo-loss dielectric-filled) Ansoft Corporation 0.00 XY Plot 1 One_Via -1.00 Coax-TSV (Si-filled) S/P Si BCB Si Si Transmission Coefficient, S12 (db) -2.00-3.00-4.00-5.00-6.00 Coax-TSV (Mixed-filled) Si -7.00 Coax-TSV (Si-filled) S/P -8.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 Freq [GHz] BCB Si Coax-TSV (Mixed-filled) 19

Outline Motivation Quantification of Some EMR Problems caused by TSVs Methods for Enhancing RF Performance of TSVs in Low Resistivity Silicon On-going Activities to Overcome TSV Design & Fabrication Challenges 20

Goal of 3D ASSM Consortium on 3D All Silicon System Module (3DASSM) Miniaturization of the entire electronic system using Si for ICs, packages, and boards. This approach is expected to result in high system performance at low cost and high reliability. Academic Partners Georgia Tech (USA) KAIST (Korea) Fraunhofer IZM (Germany) Proposing 20+ Projects & 3 Test Vehicles Thrusts Electrical Design & Test Silicon Substrate with Multilayer Wiring Low-cost TSV & Stack Bonding Embedded Thin Film Actives & Passives System Interconnects More Information: http://www.prc.gatech.edu/events/3dassm/index.htm 21

Consortium on 3D All Silicon System Module (3DASSM) Electrical Design & Test Thrust Objectives: Explore and develop design methodologies to enable ultraminiaturization and low cost hetero-integration addressing the challenges with the electrical properties of silicon. Project Project A-1: Design of Interposer with Zero SSN Project A-2: Design of Stack Bond with Vertical Shielding Project A-3: Hybrid Equalization for over 10Gbps High Speed Channel Previous Approach Minimize Noise using decaps and planes Non-coaxial TSV CPW Either active or passive Proposed Approach Eliminate noise with power trans. lines and TSV Coaxial TSV SWLS Magnetic Film Active and passive 22

Thank you very much for your attention! 23