Mani Vaidyanathan 1 Summary of Lecture Notes on Metal-Oxide-Semiconductor, Field-Effect Transistors (MOSFETs) Introduction 1. We began by asking, Why study MOSFETs? The answer is, Because MOSFETs are the most widely used type of transistor in integrated circuits (ICs), which are circuits (or even systems) built entirely on a single Si chip. We noted that historically, the dominance of MOSFETs has arisen because when used for digital logic operations, MOSFETs consume far less power than BJTs, meaning that they can be packed more densely onto a Si chip. We also commented that the recent trend is to implement analog functions with MOSFETs, and to combine them with digital circuits to create so-called mixed-signal ICs. 2. We stated our goals: (i) to understand MOSFET operation; (ii) to learn how to analyze MOS- FET circuits; (ii) to examine integrated-circuit (as opposed to discrete) MOSFET amplifiers. Physical Structure and Operation 1. We sketched a cross-section and a partial perspective view for an n-channel MOSFET. Look again at the sketch. Notice the four terminals, i.e., the gate (G), source (S), drain (D), and body (B). Some other things you should note: (a) The drain and source are made from n + -type material (where the + superscript means heavily doped ), and the body or substrate is made from p-type material. (b) The gate is made from an MOS structure, i.e., a metal-oxide-semiconductor structure, where a thin oxide layer of thickness t ox is sandwiched between the metal 1 and semiconductor surface. (c) There is a so-called channel region of length L that is situated between the source and the drain and immediately below the gate. (d) Physically, the device is symmetric; however, of the two n + regions in an n-channel FET, the one at higher potential during operation is called the drain. 2. With a picture of the structure of a MOSFET in mind, we took a qualitative look at how the device operates. Examine again the sketch we drew to show the arrangement for operation, and note the following: (a) The body is always connected to the lowest potential on a chip, which ensures that the source-body (SB) and drain-body (DB) pn junctions are always reverse biased; hence, carrier injection across pn junctions is not the mechanism for device operation. (b) The gate voltage is labeled v GS and the drain voltage is labeled v DS, with the source taken as the reference. 1 In modern MOSFETs, instead of metal, another suitable conductor, such as doped polysilicon is typically used, but for the purposes of discussion, we still use the label metal.
Mani Vaidyanathan 2 (c) Since the gate oxide is an insulator, then we must have i G 0 (1) Since the SB and DB pn junctions are reverse biased, we must also have i B 0 (2) KCL then implies that i D = i S (3) where, for the n-channel device, i D is marked as flowing into the drain terminal and i S is marked as flowing out of the source terminal. 3. In order for there to be any possibility of current flow between the source and the drain, some sort of conducting path, or channel, must exist between these points. To see how such a path could arise, we looked at creating a channel under the condition that v DS 0. Examine that discussion, and note the most important point, which is simply that to get a channel, we need the gate voltage to exceed a critical value known as the threshold voltage: v GS > V t (for an induced channel) (4) where V t is the symbol employed for threshold voltage, not to be confused with V T, which we had earlier used to represent the thermal voltage. Intuitively, it should not be too surprising that the gate voltage must be made sufficiently positive in order to create the required channel; loosely speaking, the positive gate voltage simply attracts electrons to the semiconductor surface under the gate, 2 in the region between x = 0 and x = L. 4. Under the assumption that a channel exists, we looked at the nature of current flow for small values of v DS. Read the explanation from your notes. The basic idea is that applying v DS > 0 creates an x-component of electric field within the channel that causes electrons to drift from source to drain. Since electrons flow from source to drain, do you see that i D, the conventional current flowing into the drain terminal of an n-channel MOSFET, must be positive? For small v DS, we wrote i D v DS /r DS, where r DS is the channel resistance, whose value decreases as v GS increases, since the channel becomes thicker with increasing v GS. This allowed us to show a partial plot of the expected behavior for i D versus v DS, valid for small v DS, and with v GS as a parameter. Look at the plot now. 5. With the behavior for small v DS explained, we next considered operation with increasing v DS. The first thing to understand is that since the device is physically symmetric, then at the source end, v GS induces the channel charge, whereas at the drain end, v GD induces the 2 A more precise explanation of what exactly occurs, and why a critical voltage V t is needed in order to build up an appreciable number of electrons, would require us to digress heavily into the physics of the situation, which is beyond the scope of EE 340.
Mani Vaidyanathan 3 channel charge. Now, with a positive v DS, we find that v GD < v GS, which follows since v GD = v GS v DS. Since v GD < v GS, then we get less channel charge at the drain end, i.e., the channel takes on a strictly tapered form. This explanation, by the way, is no more than a plausibility argument, so don t look for anything too deep here. If you believe that the channel is tapered, as just explained, then you should also believe that the tapering becomes more severe as v DS increases, i.e., that the channel gets squeezed near the drain end, thereby increasing its resistance. This then causes the i D versus v DS curves to bend down with v DS. These observations allowed us to expand the plot we had constructed for small v DS. Take a look at the expanded plot now. 6. As v DS is continually increased, obviously, at some point, the tapering effect discussed above will become so severe that the channel must pinch off at the drain end. We noted that this occurs, as might be expected, when v GD = v GS v DS has fallen to a point where v GD = V t (pinch-off boundary) (5) or, written another way, when v DS has increased to the point where v DS = v GS V t (alternative way to write pinch-off boundary) (6) With even higher values of v DS than the limit in the preceding equation, the channel stays pinched off, and the current i D saturates. 3 This observation allowed us to complete our plot of i D versus v DS with v GS as a parameter, which you can now examine. 7. Do you see that in the above discussion, we essentially covered the three regions of MOSFET operation, which are dubbed cutoff, triode, and saturation? Obviously, the term saturation is used in a completely different sense than with BJTs. These regions are labeled on the final plot we constructed. You should again look at that plot and note how the labels identify the regions of operation: (a) Cutoff occurs when there is no channel at all, i.e., when v GS V t. (b) Triode occurs when v GS > V t and v DS < v GS V t, so that we have a channel, and the channel is not pinched off; the second inequality here stems from the discussion leading to (6). (c) Saturation occurs when v GS > V t and v DS v GS V t, so that we have a channel, but the channel is pinched off. It may take a while for you to get comfortable with the inequalities identifying the various operating regions. That will come with practice. For now, just make sure that you can follow the arguments leading to the inequalities, and that you agree with them. If you continue to have difficulty after going through the material again, then please don t hesitate to ask me for clarification. 3 Nice try, you say. Obviously, if the channel pinches off, then the current should drop immediately to zero. Well, you are correct, so let me clarify the terminology here. When we say the channel pinches off, what we really mean is that it becomes extremely narrow but still exists. The current is then carried by the electrons in this extremely narrow or pinched off end of the channel.
Mani Vaidyanathan 4 8. Based on the qualitative description of device operation, we noted the reason for the name MOSFET. The device is a field-effect transistor or FET because its operation hinges around the electric field in the channel region, and the prefix MOS is used because of the physical structure of the gate region. 9. We wrote down the operating equations for the n-channel MOSFET, i.e., the i D -v DS -v GS relations: Cutoff (v GS V t ) : i D = 0 W Triode (v GS > V t, v DS < v GS V t ) : i D = k n L [ (v GS V t )v DS 1 ] 2 v2 DS Saturation (v GS > V t, v DS v GS V t ) : i D = 1 W 2 k n L (v GS V t ) 2 In these equations, (7) k n = µ n C ox (8) is the transconductance parameter, where µ n is the electron mobility, and C ox = ɛ ox t ox (9) is the gate-oxide capacitance per unit area, with t ox being the oxide thickness, ɛ ox = 3.9ɛ 0 being the appropriate value of dielectric constant, and ɛ 0 = 8.854 10 14 F/cm being the permittivity of free space. 10. We noted a few key items about the relations in (7). I will repeat the points: (a) In the triode region, holding v GS fixed, the i D -v DS curve is a parabola. (b) The relation for saturation can be found by substituting v DS = v GS V t, the condition for pinch-off, into the triode equation. Do you see why this must work? (c) In saturation, i D depends on the difference v GS V t, which is called the gate overdrive voltage v OV. (d) In triode and saturation, i D W/L, which is called the aspect ratio, and which can be adjusted during a circuit design in order to adjust the current without requiring a change in applied voltages. (e) Typically, W and L 0.1 µm, t ox a few nm, and V t 0.5 to 1 V. (f) For small v DS, the triode equation implies r DS = 1 k n(w/l)(v GS V t ) (10) where r DS is the channel resistance we had encountered earlier.
Mani Vaidyanathan 5 11. To complete our discussion of the operating equations, we discussed the body effect and the Early effect. (a) The term body effect refers to the fact that the body (or substrate) voltage can have an impact on the drain current i D. We stated that this dependence could be taken into account by making the threshold voltage dependent on the source-body voltage v SB, as follows: V t = V t0 + (some function of v SB which is zero when v SB = 0) (11) The key point here, as we noted, is that when v SB 0, i D will depend on v SB through V t ; on the other hand, if v SB = 0, then V t is just a number (equal to V t0 ) and i D does not depend on v SB. (b) The term Early effect describes a situation in MOSFETs similar to what we saw earlier in the course with BJTs. You can reread the appropriate part of your notes yourself. The key point is that due to channel-length modulation in saturation, i D doesn t really saturate after pinch-off, but exhibits a v DS dependence, and to account for this, we introduce a fudge factor into the equation describing the current: Saturation (v GS > V t, v DS v GS V t ) : i D = 1 W 2 k n L (v GS V t ) 2 (1 + λv DS ) = 1 ( W 2 k n L (v GS V t ) 2 1 + v ) DS V A (12) where λ = 1 V A (13) is called the channel-length modulation parameter and V A is the Early voltage. 12. To talk about MOSFETs in circuits, we need to agree on a circuit symbol. We looked at the full symbol for an n-channel FET, which includes a body terminal, and a simplified symbol, which excludes the body terminal. The simplified symbol is almost always used, with the understanding that the body terminal is connected to the most negative voltage on a chip. 13. We made a number of notes regarding the symbol, which you should review. I won t repeat them here, except to say that you should focus on the distinction between source and drain, the marked directions of current flow, and the fact that, even if the body terminal is not explicitly shown, if we have reason to believe that v SB 0, then we need to account for the body effect. 14. For completeness in our discussion on the physical structure and operation of MOSFETs, we looked at the p-channel device. The operation is analogous to an n-channel FET, but obviously we need to be careful about directions and signs. First, look at the notes you wrote down, including the drawn circuit symbols, and focus on the differences, compared to an
Mani Vaidyanathan 6 n-channel FET, with respect to the marked terminal currents and voltage polarities under normal operation. Do this carefully. You don t need to necessarily memorize anything here, but you will need to slow down until you are satisfied. 15. When you are ready, look at the lecture handout entitled, and memorize the key results. Bookkeeping for a p-channel Device 16. With the p-channel FET understood, we looked at the term CMOS, which describes the most widely used technology for manufacturing digital and low-frequency analog ICs. As we noted, it uses both n- and p-channel devices, and is hence dubbed complementary MOS or CMOS. I would guess that you have already heard this term if you haven t, then please note that this jargon is so widely recognized by electrical and computer engineers, that you should memorize it now. 17. At this stage, you should be ready to review the worked examples and tips of Seminar 6. Please do this now. Low-Frequency, Small-Signal Models 1. For amplifier applications, we need a small-signal model for a MOSFET working in saturation. We stated that we would develop one while neglecting both the body and Early effects, which would then be taken into account at the end. 2. By considering a MOSFET in a simple configuration for amplification, we first wrote down the results for the dc bias point: I G = 0 I D = 1 W 2 k n L (V GS V t ) 2 = I S V DS V GS V t (14) where the final inequality must be verified to ensure operation in the saturation region. 3. We then developed the small-signal relationships for the device. (a) We began with the small-signal condition: v gs (t) 2V OV (small-signal condition) (15) where v gs (t) is the small-signal, gate-source voltage and V OV is the dc overdrive voltage. This is the condition required to neglect distortion.
Mani Vaidyanathan 7 (b) When the small-signal condition is satisfied, we found that i d (t) = g m v gs (t), where g m is the transconductance, given by one of three possible expressions: W g m = k n L (V W GS V t ) = k n L V OV g m = 2k n W/L ID (16) g m = 2I D V GS V t = 2I D V OV The first expression gives g m in terms of k n, W/L, and the bias voltage; the second gives g m in terms of k n, W/L, and the bias current; and the third gives g m in terms of bias voltage and current. As we noted, it is also easy to prove that g m = di D dv GS where i D is given by the saturation expression in (7). (17) Q (c) We stated that the small-signal currents at the gate and source can always be written as i g (t) = 0 (18) and i s (t) = i d (t) (19) 4. To represent the small-signal relationships, we drew a couple of simplified equivalent circuits, the hybrid-π and T models. These are analogous to the circuits we had for bipolar transistors, but note that in the hybrid-π for the MOSFET, there is an open circuit between the gate and source terminals. 5. To augment our results, we then discussed the inclusion of the Early and body effects. (a) As we mentioned, the Early effect can be taken into account by the inclusion of an output resistance r o between the drain and source terminals of the hybrid-π or T models, where r o is defined by 1 r o = (20) i D / v DS Q with i D given by (12). By performing the differentiation, and assuming V A V DS, one finds r o = V A I D (21)
Mani Vaidyanathan 8 (b) We then discussed the body effect, which is a little more tricky. Please reread this part of your notes. The main point is that the body can be visualized as a type of second gate for the MOSFET. When the ac body-source voltage v bs is nonzero, it can impact the ac drain current i d, which we model through a body transconductance g mb. A generator g mb v bs is placed alongside the usual transconductance generator g m v gs in the hybridπ model; we did not discuss how to modify the T model for the body effect, mainly because it is messy if you need to take into account the body effect on the ac behavior of a MOSFET, then use the hybrid-π model with the body-transconductance generator. How do you find the body transconductance? First, you have to remember that the body voltage impacts the drain current i D through the threshold voltage V t, as specified by (11), i.e., the total, large-signal drain current i D is a function (through V t ) of the total, large-signal, body-source voltage v BS. With the existence of this implicit functional dependence, we can then define 4 the body transconductance as follows: g mb i D (22) Q v BS While this formally defines g mb, in practical situations, we simply write where χ 0.1 to 0.3. g mb χg m (23) 6. With all the elements of the small-signal models discussed, we drew the overall small-signal equivalent circuits, in both hybrid-π and T forms. Look at those circuits now. The T model, which does not include the body effect, is very similar to the one we had for BJTs. 5 The hybrid-π is more involved, because we ve included the body effect, which causes the model to have four terminals. However, if you pretend that the body is like a second gate, then you should see a symmetry in the circuit that helps you to remember its form. 7. The above discussion on small-signal modeling was for an n-channel MOSFET. To handle the small-signal modeling of a p-channel device, we wrote down a recipe without proof. I ll repeat it here: (a) Compute the dc bias point. (b) Find g m using any of the n-channel formulas in (16), but replace V GS V SG, V t V t, and V OV V SG V t. (c) Find r o = V A /I D = 1/[ λ I D ]. (d) Compute g mb = χg m, as before. (e) Use the same ac circuits, but be careful to correctly identify the source and drain of the p-channel device. 4 Even though (11) is written in terms of v SB, the body transconductance is defined in (22) by a derivative with respect to v BS. This is done by convention for simplicity in the bookkeeping. I m just telling you this so you don t worry about it. 5 Do you see the subtle difference?
Mani Vaidyanathan 9 Integrated-Circuit MOSFET Amplifiers 1. As we did with BJTs earlier in the course, we ended our discussion of MOSFETs by studying amplifiers. However, with MOSFETs, our focus was on amplifiers implemented in integrated circuits rather than with discrete components. 2. As we noted, designing amplifiers on integrated circuits poses certain constraints: (a) The moderate- to large-value resistors used in discrete amplifiers would consume too much area on a Si chip. (b) The large capacitors used for coupling and bypass functions in discrete designs are unavailable in ICs. How can amplifiers be constructed on ICs within these constraints? This was the question we then continued to examine. 3. Our first step was to understand the basic MOSFET current mirror. Look at the overall circuit we drew for a basic mirror, and note the following: (a) The arrangement of the two transistors, Q 1 and Q 2, with Q 1 employed in a diodeconnected fashion. (b) The fact that the body effect can be neglected make sure you understand why. (c) The use of a precision resistor R to help set up a reference current i REF that flows through Q 1, the diode-connected device. (d) The output current i O and output voltage v O at Q 2. 4. We performed a dc analysis of the basic mirror, neglecting the Early effect; the body effect, as already mentioned, is not present. I will not repeat the analysis here, but I will state the main conclusion: I O = (W/L) 2 (W/L) 1 I REF (24) Look back at the analysis, and make sure you can follow each step. 5. To describe the outcome (24) and the operation of the mirror in words, we wrote, The arrangement of Q 1 and Q 2 causes I O to mirror or reflect the value of I REF [to within a scale factor (W/L) 2 /(W/L) 1 ]. You should have a warm-and-fuzzy feeling about this statement. 6. We commented on how, given a resistor value R, one could determine I REF of the mirror; alternatively, for a required value of I REF, we stated how R could be found. Take a look at what we said. 7. We noted some caveats about our dc analysis of the mirror. They concern the requirement that the output transistor Q 2 remain in saturation, and our neglect of the Early effect. Quickly review these caveats.
Mani Vaidyanathan 10 8. If you understand how the current mirror works, then the concept of current steering should not be too difficult. The idea is that appropriately arranged mirrors, each with one or more outputs, can be used to steer a reference current to various parts of a circuit. Take a look at the example circuit we drew, and see if you can qualitatively follow its operation. 9. We performed an ac analysis of the current mirror. For this purpose, we considered a mirror with an ideal current source I REF above Q 1 instead of the resistor R. 10. The aim of our ac analysis was to determine the Thévenin-equivalent output resistance R out of the current mirror proper. The qualifier proper is included here because we drew the current mirror without specifying what lies above Q 2. Whatever is up there in a given application could modify the true value of R out. To emphasize this, the arrow used to label R out was drawn with a little kink that folded down towards Q 2. 11. The ac analysis itself is not too difficult, but there are a few things that might trip you up, as follows: (a) For the first time, we drew ac circuits while continuing to use the MOSFET circuit symbol, i.e., without replacing the MOSFET with its small-signal model (hybrid-π or T). This might seem a little strange to you, but as long as we follow the rules for drawing ac circuits (e.g., setting dc sources to zero), we can actually represent the MOSFET any way we want, whether it be its usual circuit symbol or one of its smallsignal models. The reason I did not replace the device with its small-signal model is because advanced circuit designers often follow this practice; from your perspective, in EE 350, you may meet ac circuits where the MOSFET has not been replaced by its small-signal model. (b) Usually, when determining R out, we would set the input ac source to zero. No input ac source is specified for the current mirror, so there is nothing to turn off. 12. Carefully follow the calculation leading to the result R out = r o2 (25) which states that the Thévenin resistance is equal to the r o of the output transistor. 13. You should now have the tools to go through Seminar 7. Please do this now. 14. With the basic current mirror understood, we then looked at IC amplifier configurations for MOSFETs. 15. The first was the common-source (CS) amplifier. Look at the discrete version first, and note the role of the resistor R D, which is needed for biasing and which acts as a type of intrinsic load for the drive or amplifying transistor Q 1. 16. Now look at the integrated-circuit version. Here, R D has been replaced by a current mirror made from the transistors Q 3 and Q 2. This has two effects. From a dc perspective, the current mirror will provide the drive transistor Q 1 with a bias current. From an ac perspective, the Thévenin output resistance of the mirror (proper) acts as a type of intrinsic load for Q 1.
Mani Vaidyanathan 11 Since this load originates from a circuit with transistors, we say that Q 1 is actively loaded and refer to the amplifier as a common-source amplifier with an active load. This is one of the deeper concepts in the course, so don t worry if you have to slow down here to fully absorb it. 17. We made a couple of notes on the actively loaded CS amplifier. (a) We said that to analyze it, and other IC amplifiers, we would (i) neglect the Early effect and neglect the body effect (even if present) for dc analysis; and (ii) include the Early effect and include the body effect (if present) for ac analysis. (b) We said that the circuit we examined for the CS amplifier is actually a partial circuit; an actual implementation would involve other components to stabilize the bias voltage V GG in the circuit, and to keep Q 1 and Q 2 in saturation (Q 3 is diode connected and hence is automatically in saturation). However, with this and other IC amplifiers, our focus in EE 340 will be to analyze the partial circuit, assuming all devices are in saturation. 18. We performed an ac analysis of the CS amplifier with active load. The key step in doing the analysis is the replacement of the current mirror by its equivalent output resistance R out = r o2, which we had calculated earlier. 6 Stop right now and make sure you understand the nature of this replacement. If it s not obvious, then you will have to think about it for a few minutes if you are still confused, then please see me or the teaching assistant for clarification; this is an important point in the course. 19. The outcome of the ac analysis was a computation of the open-circuit voltage gain, which depends on the output resistances of Q 1 and Q 2, and which we noted would be greater than the corresponding gain for a discrete CS amplifier employing a discrete resistor R D. 20. I briefly commented on using a source degeneration resistor R s in the CS amplifier. R s changes the amplifier s properties in a manner similar to what we saw with an emitter degeneration resistor R e in a discrete, common-emitter, BJT amplifier. 21. We ended by looking at the common-gate (CG) and common-drain (CD) amplifiers with active loads. We did not analyze these in detail, but noted their primary functions. Other than the use of an active load, the topologies should look familiar to you they parallel those for the corresponding, discrete, BJT amplifiers we studied earlier in the course. (a) The CG amplifier is used as a current buffer. The input is applied to the source of Q 1, the output is taken at its drain, the gate is at signal (ac) ground, and a PMOS current mirror formed by Q 3 and Q 2 is employed as an active (intrinsic) load. The body effect is present in this amplifier, and would have to be taken into account in the ac analysis (in addition to the Early effect). 6 The CS amplifier uses a PMOS current mirror, whereas we had previously analyzed an NMOS mirror; however, as you can verify yourself, the PMOS mirror behaves in an analogous fashion, and its R out is the same as what we had calculated for the NMOS mirror.
Mani Vaidyanathan 12 (b) The CD amplifier is used as a voltage buffer. The input is applied to the gate of Q 1, the output is taken at its source, the drain is at signal (ac) ground, and an NMOS current mirror formed by Q 3 and Q 2 is employed as an active (intrinsic) load. 7 The CD amplifier is also known as a source follower because the ac voltage at the source (the output) tends to follow that at the gate (the input). 22. For worked examples on IC MOSFET amplifiers, please refer to Seminar 8. Conclusions There are a couple of simple, powerful conclusions you can draw from this part of the course: 1. A MOSFET is another type of transistor; it differs from the BJT in that it operates on a fieldeffect principle. Its dc and ac behavior are qualitatively similar to those of a BJT, although the gate current is always zero, the term saturation is used in a different context, and there is an added complication known as the body effect. 2. Design constraints on an integrated circuit lead to the use of current mirrors as active loads in IC amplifiers. You can look up the details underlying these statements when you need them, but those details will serve you well only if the statements themselves resonate with you. 8 7 In the case of the CD amplifier, the primary purpose of the current mirror is from a dc perspective, i.e., to provide Q 1 with a bias current. 8 If they don t, it means something is bothering you, so please get it clarified.