Power Optimizatio for Pipelie AD ia Systematic Automatio Desig Qiao Yag ad Xiaobo Wu Abstract--A efficiet geeral systematic automatio desig methodology is proposed to optimize the power of pipelie Aalog-to-Digital overter (AD. Based o the derivatio of the total domiat power cosumptio, a hybrid search algorithm is employed to optimize the capacitace ad resolutio of each stage simultaeously. Power related factors icludig the curret optimizatio of the residue amplifiers ad the scalig dow of the stage accuracy are also ivestigated. Besides, a omputer Aided Desig (AD tool is developed to implemet the whole optimizatio process. The optimum results are depedet o the specificatios ad maufacture process. Ad guidelies for desigers to determie the miimal-power cofiguratios were derived from aalyzig of several differet precisio pipelie ADs. Especially, the optimum results of a 4-bit MS/s pipelie AD are show i detail to show the effectiveess of the proposed methodology. Idex Terms--AD, geetic algorithm, pipelie AD, power optimizatio. such situatios the optimizatio problem ca t be modeled to a GP problem. Aother efficiet approach is usig simple search egie to optimize the capacitor values ad the resolutio distributio simultaeously, which ca be replaced by a more efficiet optimizatio algorithm [5]. Ufortuately, oe of the wors metioed above itroduce a complete, geeral ad efficiet automated optimizatio method. I this paper, a efficiet ad simply implemeted tool is developed i MATLAB to miimize power cosumptio for pipelie AD o system level. Usig it, the capacitace values ad resolutio distributio could be optimized simultaeously by a hybrid search algorithm. Apart from them, the stage curret optimizatio ad scalig is also tae ito accout. Desig examples are explored to estimate the effects of such factors ad demostrate some geeral istructive desig rules. I. INTRODUTION Pipelie AD is popular choice for A/D coversio i high speed, medium-to-high resolutio applicatios, such as wireless commuicatio, video processig ad medical imagig. Nowadays, sice portability is widely demaded i these applicatios, power savig is of great importace. Although the power optimizatio ivolves may techiques, system level optimizatio is the first ad crucial step to desig a pipelie AD before goig dow to circuit details. O the other had, with the developmet of LSI techologies, automatio desig is demaded sice desig cycles are gettig short. Therefore, systematic automated desig is desirable to help desigers select the optimum cofiguratios quicly for further ivestigatio uder the give specificatios ad costraits. May wors have bee doe to reduce the power o system level for pipelie AD. These wors maily ivolve resolutio distributio ad capacitor scalig dow, showig some coditioal desig guidelies. For istace, it has bee derived that.5-bit per stage resolutio is preferred i the pipelied architecture if all the substages are idetical []. Ad the scalig factor, while it is cosidered as a costat oe to scale dow the stage uit capacitor sizes, is proved to be proportioal to the resolutio per stage if each stage has the same resolutio []. Besides, assumig a predefied oise distributio, it is proved that to resolve more bits i the frot stages is preferable choice [3]. Some other wors have advaced the automatio desig. It is worthy of metioig that geometric programmig (GP could be used to optimize power ad area of pipelie ADs simultaeously [4]. However, it s ot suitable for architectures employig o-idetical substages sice i The authors are with the Istitute of LSI Desig, Zhejiag Uiversity, Hagzhou, 37, hia. Emails: yagqiao@vlsi.zju.edu.c, wuxb@vlsi.zju.edu.c. II. ARHITETURE OF PIPELINE AD A geeral architecture of pipelie AD is show i Fig. It ca be see that the overall coversio process is broe up ito multi-step quatizatio, which is performed by a cascade of low resolutio sub-ads. Each stage except the last oe performs a coarse A/D coversio ad geerates the residue sigal for the followig stages, resolvig some segmet of the whole digital output word. The basic operatios performed i each stage except the last oe iclude samplig ad holdig, low-resolutio aalog-to-digital coversio, low-resolutio digital-to-aalog coversio, subtractio ad amplificatio. These operatios ca be easily implemeted with switched-capacitor circuits i MOS techology. I practical implemetatio, the coarse A/D coversio is usually coducted by a low-resolutio flash AD ad the rest operatios are doe with a sigle switched-capacitor bloc called Multiplyig Digital-to-Aalog overter (MDA. The last stage oly cotais a flash AD, for it does t eed to geerate residue sigal. I Iput S/H Stage i Stage Sub- AD Stage Sub- DA Stage NS (sub-ad NS (NS-T (NS-T NS T delay delay delay T delay NS Digital correctio N - MDA SH out Fig. Geeral architecture of a NS-stage pipelie AD
A typical switched-capacitor MDA is comprised of a capacitor-array, some switches ad a residue amplifier (RA. Two o-overlappig cloc phases are eeded per coversio. As illustrated i Fig., Φ is for samplig ad sub-a/d coversio, while Φ is for subtractio ad amplifyig. Durig Φ, the capacitor-array of the MDA is coected to the iput sigal, beig charged while the flash AD is performig a coarse quatizatio. At the ed of Φ, the iput sigal is sampled ad the quatizatio result is ecoded to cotrol the switches of the MDA i the ext phase. Durig Φ, the feedbac capacitor is switched to the RA output maig a egative feedbac loop. The samplig capacitors are switched to ref,, or -ref accordig to the cotrol sigal geerated i Φ, which actually performs the sub-d/a coversio. Thus the correspodig aalog sigal is subtracted from the iput sample, amplified bac to the full-scale referece level ad held i the feedbac capacitor for the followig stage to process. i, s, i f s,,( s = f i ref ref ref ref s,,( s Fig. Operatios of stage III. POWER ANALYSIS f o, = ( i, DA The bias circuits, logic circuits ad other auxiliary circuits such as refereces ad cloc geerators oly cotribute a small portio to the overall power compared with the pipelied coversio stages. Therefore i a pipelie AD, MDAs ad sub-ads domiate the power cosumptio. Besides, accordig to [] [6], the power cosumed by each comparator i the sub-ad is proportioal to that cosumed by the MDA i the same stage. Thus the power cosumptio of sub-ad ca be estimated referrig to that of the correspodig MDA. Hece, represetig power by curret cosumptio, the total power cosumptio ca be estimated by the curret cosumed by MDAs. I order to correct errors itroduced by comparator offsets, i this paper oe overlappig bit is used i each stage except the last oe, i.e. for stage, if a -bit biary code is geerated by the sub-ad, the correspodig amplifier gai is G =. Adoptig digital correctio, the umber of comparators of the sub-ad i stage is (, NS (NS is the stage umber.. I the last stage, the comparator umber is ( NS [8]. Note that the power cosumed by a MDA actually goes to the employed RA. Assumig the curret ratio of a sigle comparator to the correspodig RA is R, thus for a NS-stage pipelie AD, the total curret cosumptio is obtaied from I tot NS I = NS RA, ( ( R ( Ic, NS o,, ( where I c,ns is the curret of the comparator i the last stage, which ca be estimated idetical to that of the comparator i the precedig sub-ad. I. OPTIMIZATION ONSIDERATIONS A. urret Optimizatio of RA Requirig high dc gai as well as large badwidth maes RA desigs the critical part i MDA. The gai-boostig techique is preferred to achieve large gai-badwidth products [6][7]. I most of the cases, RA ca be modeled as a sigle-pole system, the total curret cosumed by which is proportioal to the tail curret of the iput trasistors. Defiig, o, ad β as the sigle-eded full-scale voltage, the effective gate-drivig voltage ad the feedbac factor respectively, if is smaller tha o /β, the output of RA will ot slew. Otherwise it will slew util the amplifier returs to the liear settlig state. Therefore, the required bias curret of a sigle-pole RA is estimated by I RA, opt ol l, βtcl σ β ol o (l βtcl β σ o, o β, ( o β where L is the load capacitor, T LK is the period of the samplig cloc, ad σ is the allowed settlig error due to the fiite gai badwidth of the RA. L is varied whe the substages are o-idetical. With purely capacitive load, the RA employed i a switched-capacitor MDA ca be implemeted with OTA which is oly eeded to wor i the amplifyig phase [3]. Fig.3 shows a simplified sigle-eded versio of A model of the RA employed i stage. s,,( s op _ i, = s s, i i= f op _ out,, Fig.3 Sigle-eded versio of A model of RA i the amplifyig phase The capacitive load of stage ca be calculated accordig to Fig. 3 from ( =, (3 s op_ i, f op_ out,, s op_ i, f where s, f, op_i,,, ad op_out, are the samplig capacitace, the feedbac capacitace(or the uit capacitace of the capacitor-array, the iput capacitace of OTA, the iput capacitace of the followig stage, ad the output capacitace of OTA respectively. It is otable that whe the -th residue stage is i hold mode, the (l-th stage wors i samplig mode. For a -bit residue stage, based o the followig equatios: s f =, (4
, = f ( ( c,, (5 op _ i, = a, (6 f op _ out, = b ( s s op _ i, op _ i, equatio (3 ca be rewritte as ( a f = ( b (, c f ( a f f, (7, (8 where a represets the ratio of op_i, to f, c, is the iput capacitor of each comparator i the sub-ad of stage, ad b represets the excess portio cotributed by op_out,. Actually, a ad b represet speed-depedet factor sice the effect of parasitic-loadig is varied with coversio speed[7]. Equatio (5 demostrates that, is comprised of the iput capacitaces of the MDA ad the flash AD of the ext stage. For stage (NS- the capacitive load is much smaller: ( a NS NS f ( NS NS NS = ( b NS NS ( ans c, NS. (9 The output of the OTA should settle to the desired value which depeds o the stage accuracy requiremets. σ i ( represets the stage accuracy requiremet, which is assumed idetical for each stage i [5]. However, it does t completely optimize the power sice the requiremets get relaxed as a sigal goes dow the pipelied architecture. For each stage, error portio should be smaller tha.5lsb of the remaiig resolutio i the worst case [6], i.e. for stage, σ <, ( N, r where N r, is the remaiig resolutio after stage. Remidig that the feedbac factor for stage is β, ( a = f, = s op i, _, f, thus the curret cosumptio of RA i stage becomes o o ( a ( Nr, l, ( a Tcl IRA, Nr, o L( a ( a o o (l, ( a Tcl o( a ( a f ( b (,,, NS c f a L, = ( a f ( b (, = c, NS a, ( where the settlig error is required less tha.5lsb of the remaiig resolutio. B. Thermal Noise It ca be observed from ( that the smaller the capacitaces are, the less power RA will cosume. However, give the SNR, the miimum capacitace is costraied by thermal oise ad process. Process determies the miimum achievable capacitace that satisfies the matchig requiremets, which ca t be optimized through systematic desig. O the other had, thermal oise maily comes from RA ad the o-resistaces of switches. For stage, the iput-referred oise of the switched-capacitor RA with a structure lie Fig.3 ca be approximated as [], = KT 4 f 4 KT N ( ( = ( ( β 3 β 3 f f s f opamp, (3 where N opamp is the oise factor depedet o the topology of RA. The total iput-referred thermal oise of the coverter is,,3,4, NS, t =, L NS G G G G GG3 G =. (4 Sice the last stage does t eed MDA, the thermal oise is igored here. To guaratee the desired overall resolutio, the thermal oise is required less tha the quatizatio oise, i.e. for a N-bit AD, the coditio (, t (5 N must be satisfied. Thus the resolutio per stage ad the capacitor sizes must be chose carefully to satisfy the thermal oise requiremets. Sice the oise i later stages is suppressed by amplifiers i the proceedig stages, capacitor sizes ca be scaled dow to reduce power.. apacitor Scalig As said, capacitor sizes ca be scaled dow alog the pipelied architecture sice oise i later stages is suppressed by proceedig stages. Power is reduced i later stages due to reduced load capacitaces but icreased i frot stages to compesate for the icreased oise i later stages. Thus for a determied cofiguratio, there is a optimum combiatio of the uit capacitace per stage which miimizes the power. I this paper geetic algorithm (GA is adopted to solve this multi-variable optimizatio problem. GA is a id of radom search techologies used i computig to fid exact or approximate solutios to optimizatio ad search problems, which is ispired by harles Darwi s theory about evolutio. It has bee utilized to optimize aalog circuits i some published wors [][3]. Give some reasoable ad ecessary costraits, GA ca fid the solutios efficietly. Detailed descriptio of GA is out of the scope of this paper. Defiig x as the uit capacitace ratio of the (th stage to the th stage ad ( ca be rewritte as ol, o ( a ( Nr, l, ( a,(6 Tcl IRA, Nr, ol ( a ( a o o (l, ( a Tcl o( a ( a ( ( b x x (,, NS j c a j= L, = ( a ( b = x (,, NS j c a j=
where is the uit capacitace of the first stage. osiderig two extreme situatios, i.e. o scalig is used or each stage cotributes equally to the total thermal oise, x is limited by G x. (7 Besides, the capacitaces i each stage should ot smaller tha the miimum value mi which is costraied by the matchig accuracy requiremets (depedet o DNL ad process, ad should ot larger tha the acceptable value max set by the desigers, i.e. mi x = j j max NS, (8 substitutig (5 for I RA, i (, the optimizatio problem becomes: Give a series of desig parameters, fid the optimum x ad uder the costraits (3, (4, (5,(7 ad (8, i order to miimize (ad(6, where for a NS-stage pipelie AD, x=[, x, x, x 3, x, x NS- ] ad =[,, 3,, NS ]. The whole algorithm is realized i MATLAB as a part of the developed AD tool. D. The Frot-ed S/H So far power cosumed by the mai coversio blocs has bee aalyzed. Actually, there is aother importat factor ot covered yet. For better performace of AD especially whe the frequecy of the samplig cloc is very high, a dedicated iput sample-ad-hold (S/H stage is required i the frot ed as show i Fig.. This stage itroduces cosiderable power which is udesirable. Some methods has bee proposed to remove the frot-ed S/H stage i relatively low-resolutio low-speed cotext [9][]. I this paper power is optimized with ad without the frot-ed S/H stage. The flip-aroud architecture is chose for the frot-ed S/H as adopted i [4].. OPTIMIZATION A. Optimizatio Methodology learly see from previous aalysis, i order to estimate the power cosumptio of a pipelie AD, some parameters must be determied first, such as the overall resolutio, the speed-depedet factor, the resolutio distributio, the uit capacitace i each stage etc. For a give specificatio, the systematic optimizatio problem is to choose the resolutio, the uit capacitace value ad the curret of RA for each stage to achieve the lowest power uder the predefied costraits. As ( ad (6 show, the total curret cosumptio has a complex relatioship with the resolutio distributio ad the stage uit capacitaces, thus it s difficult to obtai the optimum cofiguratio via qualitative aalysis or derivative calculatio. I this paper, the optimum cofiguratio is obtaied through computer-aided computatio. By combiig exhaustive search algorithms with GA to explore all the potetial cofiguratios, the resolutio distributio ad capacitor sizes are optimized simultaeously. Based o the equatios derived previously, the hybrid search algorithm is implemeted with a efficiet AD tool, which is developed i MATLAB. Usig this tool, the whole cofiguratio space of the AD determied by the overall resolutio is explored for miimum power implemetatio i the five optimizatio coditios illustrated i Fig.4. The factors cocerig above optimizatio cosideratios are ivestigated i the five coditios. This tool cotais a cofiguratio auto-geerator ad five processig sub-blocs selected by the optimizatio coditio set by desigers. As see from Fig.4, i the first three blocs, i.e. NSH_IA_NS (Without frot-ed S/H, Idetical stage Accuracy requiremets, No-Scalig apacitors, NSH_DA_NS (Without frot-ed S/H, Differet stage Accuracy requiremets, No-Scalig apacitors, ad NSH_DA_S (Without frot-ed S/H, Differet stage Accuracy requiremets, Scalig apacitors, the frot-ed S/H stage is ot employed i the pipelied architecture. The last two blocs, SH_DA_ NS ad SH_DA_ S is the same with NSH_DA_NS ad SH_DA_NS respectively except adoptig the frot-ed S/H stage. The iput parameters for this tool are depedet o specificatios ad maufacture process, icludig N (the overall resolutio,, o, N opamp, mi, max, c (the iput capacitace of a sigle comparator, R, a(the vector of a s, b(the vector of b s, opt(optimizatio coditio ad T LK. c ad R are defied as vectors so that the iput capacitace of a sigle comparator ad the curret ratio ca be set idepedetly i differet substages. Fig.4 Flow chart of the proposed optimizatio methodology B. Optimizatio Examples Usig the proposed approach, to 5-bit, MS/s pipelie ADs are explored i the five coditios. Note that the resolutio per stage is hardly larger tha 5 bits i practice desig due to the comparator accuracy costraits [6]. Thus the resolutio per stage ca be, 3, 4 or 5 bits with oe overlappig bit. The values of other parameters used i the automated desig are show i TABLE I.
TABLE I Parameters used i the optimizatio Parameter alue commets Sigle-eded full-scale voltage o. Effective gate-drivig voltage N opamp Noise factor of the OTA mi.pf Miimum capacitace max 5pF Maximum capacitace c 3fF Iput capacitace of comparator R.5 urret ratio a Speed factor, the vector of a s b Speed factor, the vector of b s T LK s Samplig cloc period Fig.5 illustrates the optimized total curret cosumptio versus the overall resolutio i differet coditios. Without the frot-ed S/H, the miimum capacitace used here already satisfies the oise requiremets for - bits. O the other had the required capacitace is larger tha the acceptable value for 5 bits with the frot-ed S/H. Thus the capacitor scalig is ot doe i such cases. It ca be observed that the icreasig rates of the curret cosumptio are varied i the five optimizatio coditios, which meas that the ifluece levels of the factors discussed i the optimizatio cosideratios are quite differet. The effect of stage accuracy scalig dow becomes isigificat with the icreasig of resolutio. As Fig.5 demostrates, capacitor scalig is ecessary whe the frot-ed S/H is used; otherwise power cosumptio is icreased sharply especially i high resolutio cases. A compariso of the effects of differet factors o power reducig is give i TABLE II. omalized curret comsumptio 9 8 7 6 5 4 3 NSH-IA-NS NSH-DA-NS SH-DA-NS NSH-DA-S SH-DA-S 3 4 5 resolutio (bits Fig.5 The optimized total curret cosumptio versus the overall resolutio i five optimizatio coditios TABLE II Power reducig percetage of differet factors Factor Percetage Stage accuracy 8%-% apacitor scalig without S/H 8%-6% apacitor scalig with S/H 46%-78% The optimum cofiguratio is varied with the optimizatio coditios. TABLE III gives the optimum cofiguratios of 4 bits i five optimizatio coditios. From the power cosumptio poit of view, it s desirable that icreasig the resolutios of the first ad the last stages while resolvig bits i other stages. Fig.6 gives a compariso of the stage curret betwee the optimized ad the traditioal.5-bit/stage cofiguratios of 4 bits i the optimizatio coditios of NSH_DA_S ad SH_DA _S (with oe overlappig bit, the effective resolutio of -bit/satage is.5-bit/stage.. As it shows, if the resolutio of the first stage is properly chose, the power cosumptio of the followig stages ca be reduced greatly while oly a little power may be icreased i the first stage. O the other had, the umber of stages will decrease by resolvig more bits i the last stage which adds little load capacitaces to the proceedig stage, thus the total power is reduced. The result is supported by [4], which accords with the geeral architecture described i this paper. It also ca be observed that the curret cosumptio is domiated by the frot stages. Fig.7 shows the compariso of the stage uit capacitace correspodig to Fig.6. As see from Fig.6-7, the frot-ed iput S/H itroduces cosiderable power ad area i the frot stages. Fig.7 shows that the capacitor scalig is stopped whe the miimum capacitace is reached. It ca be see that the capacitor sizes are greatly reduced i the optimized cofiguratios compared with the traditioal oes. To illustrate the effect of resolutio distributio o power optimizatio, Fig.8 gives a compariso of the total curret cosumptio of some represetative cofiguratios of 4 bits i the optimizatio coditios of NSH_DA_S. It ca be see that the cofiguratio of 4---------3 cosumes the miimum power. TABLE III The optimum cofiguratios of 4 bits i five optimizatio coditios (with oe overlappig bit Optimizatio coditios Optimum cofiguratio NSH_IA_NS [5 5 ] NSH_DA_NS [4 5] NSH_DA_S [4 3] SH_DA_NS [3 5] SH_DA_S [4 3] bias curret of RA (ma 6 5 4 3 (NSH-DA-S (SH-DA-S 43(SH-DA-S 43(NSH-DA-S 3 4 5 6 7 8 9 stage umber( reprets the frot-ed SH Fig.6 ompariso of bias curret of RA betwee the optimized ad.5-bit/stage cofiguratios of 4 bits (i NSH_DA_S ad SH_DA _S
uit capacitace (pf Fig.7 ompariso of stage uit capacitace betwee the optimized ad.5-bit/stage cofiguratios of 4 bits (i NSH_DA_S ad SH_DA _S curret cosumptio (ma 5 5 5 3 4 5 6 7 8 9 stage umber( reprets the frot-ed SH 7 6 5 4 3... 33...3 3... 3...3 (NSH-DA-S (SH-DA-S 43(SH-DA-S 43(NSH-DA-S 43... 4... 4...3 5... 3333 433... 3 4 5 6 7 8 9 cofiguratio umber Pipelied Aalog-to-Digital overter i.µm MOS, IEEE Joural of Solid-State ircuits, ol. 3, No. 3, Mar. 996, pp. 94-33. [3] J. Goes, J.. ital, J. E. Fraca, Systematic Desig for Optimizatio of High-Speed Self-alibrated Pipelied A/D overters, IEEE trasactios o circuits ad systems II: Aalog ad digital sigal processig, ol. 45, No., Dec.998, pp. 53-56. [4] M. Hersheso, "Desig of pipelie aalog-to-digital coverters via geometric programmig," i Proc. of IEEE Itl. of o omputer Aided Desig,, pp. 37-34. [5] Reza Lotfi, Mohammad Taherzadeh-Sai, M Yaser Azizi ad Omid Shoaei, Systematic Desig for Power Miimizatio of Pipelied Aalog-to-Digital overters, i Proc. Of Iteratioal oferece o omputer Aided Desig (IAD, 3, pp. 37-374. [6] hag-hyu ho, A Power optimized pipelied aalog-to-digital coverter desig i deep sub-micro MOS techology, Ph.D thesis, Georgia Istitute of Techology, 5. [7] Yu hiu, P. R. Gray, A 4-b -Ms/s MOS Pipelie AD with over -db SFDR, IEEE Joural of Solid-State ircuits, ol. 39, No., Dec. 4, pp.39-5. [8] S. H. Lewis, -b -Msample/s aalog-to-digital coverter, IEEE Joural of Solid-state ircuits, ol. 7, No.3, March 99, pp.35-358. [9] Dog-Youg hag, Desig Techiques for a Pipelied AD without Usig a Frot-Ed Sample-ad-Hold Amplifier, IEEE trasactios o circuits ad systems I: regular papers, ol. 5, No., Nov.4, pp. 3-3. [] ao Jumi, he Zhogjia, Lu Wegao ad Zhao Baoyig, A Low Power -Bit Msamples/s Pipelied AD, Iteratioal oferece o Sigal Processig Systems (ISPS, 9, pp. 77-8. [] T. ho, Low-power Low-voltage, Aalog-to-Digital oversio Techique usig pipelied architectures, Ph.D thesis, Uiversity of aliforia, Bereley, 995. [] N. Paulio, J. Goes ad A. Steiger-Garcao, Desig Methodology for Optimizatio of Aalogue Buildig-Blocs usig Geetic Algorithms, IEEE ISAS,, pp.435-438. [3] B. az et al, A Geeral-purpose Kerel based o Geetic Algorithms for Optimizatio of omplex aalog circuits, Proc. IEEE MWSAS,, pp.83-86. [4] Wehua Yag, Da Kelly, Iuri Mehr, Mar T. Sayu ad Larry Siger, A 3-34-mW 4-b 75-Msample/s MOS AD With 85-dB SFDR, IEEE Joural of Solid-State ircuits, ol. 36, No., Dec., pp. 93-936. Fig.8 Total curret cosumptio compariso of differet cofiguratios of 4-bit pipelie AD i NSH_DA_S I. ONLUSIONS By aalyzig the power sources ad optimizatio cosideratios of a switched-capacitor pipelie AD, a optimizatio methodology is proposed for the systematic automatio desig. The mai factors related to reducig power are ivestigated usig a developed AD tool, i which optimizatio is costraied by the iput parameters depedet o the specificatio ad maufacture process of the AD. to 5-bit ADs are explored to get some istructive desig rules ad the optimizatio results of a 4-bit, MS/s pipelie AD are show i detail. AKNOWLEDGMENT This paper is sposored by the Natioal Natural Sciece Foudatio of hia uder grat No. 696. It also gais support from the Aalog Devices, Ic. (ADI. The authors would lie to tha Mr. Bill Liu, the seior egieers of ADI ad his colleagues, for their useful discussios ad istructio. REFERENE [] S. H. Lewis, Optimizig the stage resolutio i pipelied, multistage, aalog-to-digital coverters for video-rate applicatios, IEEE trasactios o circuits ad systems II: Aalog ad digital sigal processig, ol. 39, No.8, Aug.99, pp. 56-53. [] D. W. lie, P. R. Gray, A Power Optimized 3-b 5Msamples/s