High-Speed Serial Interface Circuits and Systems Design Exercise4 Charge Pump
Charge Pump PLL ɸ ref up PFD CP LF VCO down ɸ out ɸ div Divider Converts PFD phase error pulse (digital) to charge (analog). Charge is proportional to PFD pulse widths. Q cp = I up * t up I down * t down Q cp is filtered and integrated in low-pass filter. 2
Review of Charge Pump PLL 3
Basic Charge Pump M2 M4 M3 M1 Charge pump circuit consists of 2 current sources and 2 switches. 4
Current Mismatch M2 A PFD M4 I M3 B M3 I M4 Net Current M1 t Up & down current should be same. Current mismatch results in static phase offset, which results in periodic ripple on the control voltage. 5
Current Mismatch is changed according to locking voltage. Current mismatch is caused by channel length modulation. M2 Equal nmos and pmos current over entire range. Reduce phase error. M4 Drain Source M3 Gate nbias Gate M1 Source Drain I D I D I D Channel length modulation Channel length modulation 200uA V DS V DS /2 Available region V DS 6
Basic CP Simulation PMOS size (2 개동일 ) Length : 180 nm Width : 5.2 um NMOS size (2 개동일 ) Length : 800 nm Width : 5.1 um Voltage : 0.9 V Voltage : 0.9 V Target charge pump current Current : 200 ua Current Monitor 7
Simulation Condition Simulation condition setting Choose analysis Analysis : DC Design variable : cont Sweep range : 0 ~ 1.8 Sweep type : Linear Step size : 0.1 Enabled check OK 8
Plot simulation results (Current) Simulation Results Results Direct Plot Main Form Function : current Select : terminal Add to outputs check Schematic node choice DC symbol (+) node click OK 9
NMOS Current M2 I D 1.8V (OFF) M4 (0.9V) : 199.94uA (1.8V) : 200.94uA 1.8V M3 I D : 1.09uA M1 10
PMOS Current M2 I D 0V M4 (0V) : 204.30uA (0.9V) : 199.45uA 0V (OFF) M3 I D : 5.38uA M1 11
NMOS & PMOS Current M2 I D PMOS current NMOS current 0V 1.8V M4 M3 M1 : 0.5V I D : 15uA : 0.9V I D : 0.5uA : 1.3V I D : 23uA 12
PMOS NMOS Current M2 I cont 0V M4 : 0.5V I cont : 15uA NMOS current 1.8V M3 M1 PMOS current : 0.9V I cont : 0.5uA : 1.3V I cont : 23uA 13
Leakage Current 1.8V (OFF) M2 M4 I cont : 0.5V I cont : 11.5pA : 0.9V I cont : 3.8pA NMOS leakage 0V (OFF) M3 M1 PMOS leakage : 1.3V I cont : -2.2pA 14
Reducing Mismatch using Replica Replica Circuit Mp1 Mp1 Mp2 Vss + AMP - Mp2 Cont Mn1 Mn1 Mn2 Mn2 15 Vss
Design Example Charge pump circuit - Supply voltage: 1.8V - Current of charge pump: 200uA ± 10uA - Current mismatch: <150nA with range of V cont larger than 0.8V 16
VCVS (OpAmp) Voltage gain : 1000 Maximum output voltage :1.8V Simulation Schematic Minimum output voltage : 0V RC Filter of OpAmp Resistor : 1Kohm Capacitance : 1nF Replica circuit Load Charge pump size same Capacitance : 200pF Voltage : 0.9V 17
NMOS Current Mp1 Mp1 I D Mp2 Vss + AMP - 1.8V (OFF) Mp2 Cont Mn1 1.8V Mn1 Mn2 Mn2 Vss 18
PMOS Current Mp1 Mp1 I D Without FB With FB Mp2 Vss + AMP - 0V Mp2 Cont Mn1 0V (OFF) Mn1 Mn2 Mn2 Vss Change PMOS current though the feedback. 19
+ AMP - NMOS & PMOS Current Mp1 Mp1 I D PMOS current NMOS current Mp2 Vss 0V Mp2 Cont Mn1 Mn2 Vss 1.8V Mn1 Mn2 : 0.5V I D : 0.09uA : 0.9V I D : 0.03uA : 1.3V I D : 0.12uA NMOS and PMOS currents are equalized through the feedback system. 20
NMOS PMOS Current Mp1 Mp1 I cont Mp2 Vss + AMP - 0V Mp2 Cont Without FB With FB Mn1 1.8V Mn1 : 0.9V I cont : 0.03uA Mn2 Vss Mn2 : 0.5V I cont : 0.08uA : 1.3V I cont : 0.12uA NMOS and PMOS currents are equalized through the feedback system. 21
Homework Design 500uA (±20uA) charge pump with replica circuit. Without replica circuit, verify and plot pmos and nmos current waveforms with respect to cont voltage. Current mismatch : less than 60uA (cont voltage range : 0.5V ~ 1.3V) With replica circuit, verify and plot pmos and nmos current waveforms with respect to cont voltage. Current mismatch : less than 400nA (cont voltage range : 0.5V ~ 1.3V) Charge pump specification VDD supply voltage : 1.8V voltage : 0.9V Charge pump current : 500uA (±20uA) at nbias voltage 0.9V Due: Next design class (Hardcopy) 22