Lecture #6: Analog-to-Digital Converter

Lecture #6: Analog-to-Digital Converter All electrical signals in the real world are analog, and their waveforms are continuous in time. Since most signal processing is done digitally in discrete time, devices that convert an analog waveform into a stream of sampled discrete digital numbers or the digital number stream back into an analog waveform are needed. The former is called analog-to-digital converter (ADC or A/D), and the latter is called DAC or D/A. Antialias Sample A/D time freq time T=1/f S f S 2f S freq time freq Fig. 6.1: ADC system and its spectrum. Quantization process is sketched in Fig. 6.1. To meet the Nyquist requirement, the input signal should be band-limited within half the sampling frequency. Sampling is the multiplication of the input signal with the impulse sequence, whose frequency response also repeats every f S. Since the multiplication in the time domain is the convolution in the frequency domain, the sampled waveform spectrum repeats as sketched. Wanted Unwanted freq freq f S 2f S 3f S 4f S freq Fig. 6.2: Aliasing when not band-limited. Bang-Sup Song 1 ECE163

This sampling effect is further explained in Fig. 6.2, when the input signal is not band-limited. For example, if any unwanted signal exists at 3f S, it will be aliased into all signal bands after sampled as shown. So the purpose of the anti-aliasing filter placed before S/H is obvious. Quantization Noise Resolution is a term used to describe a minimum amount of voltage or current that ADC/DAC can resolve. Resolution is usually quoted by the number of binary bits representing the analog input. The quantization step is due to the finite number of bits used in ADC/DAC. In an N-bit ADC, the minimum input analog voltage V REF /2 N can be represented with a full-scale input range of V REF. That is, a total of 2 N digital codes are available to represent the continuous analog input from to V REF as explained in Fig. 6.3. 1-bit 2-bit N-bit V REF Analog Range 1 1 1 1 Binary Thermometer 1 out of N Gray 1 1 1 1 1 1 1 1 1 1 Fig. 6.3: ADC quantization and digital representation. Similarly, in an N-bit DAC, 2 N input digital codes can generate V REF /2 N distinct analog output levels within V REF. The minimum resolvable step is defined as follows. V REF N = (6.1) 2 The finer the step is, the higher the resolution is. The step gets smaller as N increases. Analog-to-digital conversion process is to get a digital representation of an analog input. D = V IN = V IN 2 N (6.2) V REF where the bracket [ ] represents an operation of rounding to a lower integer. Digital number can be represented in different forms as shown in Fig. 6.4. Among them, the Bang-Sup Song 2 ECE163

binary number system is most common. For example, when represented in a binary number like 1 1, the first digit is the most significant bit (MSB), and the last one is the least significant bit (LSB). 1 Digital Output V REF Analog Input Q Error V REF Fig. 6.4: ADC quantization error. The transfer function of ADC is made of uniform steps as shown in Fig. 6.4. As the continuous analog input is quantized, the quantization error appears as a white noise uniformly spread within the Nyquist band. Assuming that the magnitude of quantization error is independent of the input and random between /2 and /2, the mean squared quantization noise is estimated as follows. q 2 = 1 / 2 / 2 x 2 dx = 2 12, q2 = 2 12 (6.3) Digitized Spectrum Signal Noise = 2 12 Digitized Spectrum f S /2 Signal Noise = f S 2 12 f BW f S /2 Fig. 6.5: Quantization noise spectrum at two sampling rates. Bang-Sup Song 3 ECE163

Signal-to-Noise Ratio UNIVERSITY OF CALIFORNIA, SAN DIEGO Signal-to-noise ratio (SNR) is defined as a ratio of maximum signal power to in-band uncorrelated noise. Quantization noise is evenly spread over the Nyquist bandwidth (half the sampling frequency) as shown in Fig. 6.5. The SNR of an ideal ADC/DAC is therefore approximated as follows. SNR = SignalPower NoisePower = V REF 2 2 12 1logSNR = (6.2N +1.76)dB ~ (6N +1.8)dB 2 2 = 3 2 22N (6.4) For example, an ideal 16b ADC/DAC has an SNR of about 97.8dB. In-band quantization noise decreases by 3dB when the sampling rate is doubled. When over-sampled, SNR within the signal band can be made higher. ADC resolution is usually characterized in terms of SNR, but SNR accounts only for the uncorrelated noise. Real noise performance is better represented by signal-to-noise and distortion ratio (SNDR, SINAD, or TSNR), which is the ratio of the signal power to the total in-band noise power including harmonic distortion. Also a slightly different term is often used in place of SNR. Dynamic range (DR) is defined as the power ratio of the maximum signal to the minimum signal. The minimum signal is defined as the smallest signal when SNDR is db while the maximum signal is the full-scale signal. In practice, the ADC performance is not only limited by the quantization noise but also by non-ideal factors such as noises from circuit components, power supply coupling, noisy substrate, timing jitter, settling, and nonlinearity, etc.. The SNR of non-ideal ADC/DAC is thus lower than the ideal DR because the noise floor can be higher with large signals. S SFDR D SNDR = S N + D N f S /2 ENOB = SNDR 1.76 6.2 SFDR = S max Max Spurious Tone DR = S max S min @ SNDR=dB Small Signal Cases: INL limited DNL limited Fig. 6.6: Other definitions. Bang-Sup Song 4 ECE163

An alternative definition of the resolution is the effective number of bits (ENOB), which is derived from the definition of SNDR. ENOB = SNDR 1.76 6.2 (Bits) (6.5) Usually, ENOB is defined when the input frequency is half the sampling frequency. Spurious-free dynamic range (SFDR) is defined as the ratio of the carrier to the highest spurious tone. These definitions are graphically explained in Fig. 6.6. Differential and Integral Non-Linearity The input/output ranges of an ideal N-bit ADC/DAC are equally divided into 2 N small unit segments, and one least significant bit (LSB) in the digital code corresponds to an analog voltage step of V REF /2 N. Static ADC/DAC performance is characterized by the differential nonlinearity (DNL) and integral nonlinearity (INL). DNL is a measure of deviation of an actual ADC/DAC step from the ideal step of one LSB, and INL is a measure of deviation of the ADC/DAC output from the ideal straight line drawn between two end points of the transfer characteristic. D D DNL A INL A Fig. 6.7: DNL and INL definitions. Both DNL and INL are measured in the unit of one LSB. In practice, the largest positive and negative numbers are usually quoted to specify the static performance. These DNL and INL definitions for ADC are defined as shown in Fig. 6.7. DNL = DNL (LSB), INL = INL (LSB) (6.6) Several different definitions of INL may result depending on how two end points are defined. In some systems, two end points are not exactly and V REF. Non-ideal reference point causes an offset error while non-ideal full-scale range gives rise to a gain error. In most applications, the offset and gain errors do not matter, and the integral linearity can be better defined in a relative measure using a straight-line linearity concept rather than the end-point linearity. The straight line can be defined as two end points of the actual transfer function, or as a theoretical straight line adjusted for the best fit. The former is sometimes called the end-point linearity while the latter is called the beststraight-line linearity. Both in ADC/DAC, the output should increase over its full range Bang-Sup Song 5 ECE163

as the input increases. That is, the negative DNL should be smaller than 1LSB for any ADC/DAC to be monotonic. Monotonicity is critical in most applications - in particular digital control, audio, or video applications. Thermometer V ref V in 1 Comparators 1-of-2 N 1 V dd Binary Encoder 1 1 V dd b1 b Fig. 6.8: 2b flash ADC. Flash ADC The most straight-forward way of making an ADC is to compare the input with all the divided levels of the reference simultaneously. Such a converter is called a flash ADC, and the conversion occurs in one shot like a flash. The flash architecture is the fastest among all ADCs. The 2b flash ADC is explained in Fig. 6.8, where divided reference voltages are compared to the input. The binary encoder is needed because the output of the comparator bank is thermometer-coded. The resolution is limited both by the accuracy of the divided reference voltages and by the comparator resolution. Resistorstring DACs can provide references as the number of bits grows. Since it is fullyparallel, only one comparison cycle is needed. In practical implementations, the limit is the exponential growth in the number of comparators and resistors. For example, an N-bit flash needs 2 N 1 comparators and 2 N resistors. Furthermore, for Nyquist-rate sampling, the input needs a S/H amplifier to freeze the input for comparison. As the number of bits grows, the comparator bank presents a significant loading to the input S/H. This contradicts with the speed advantage given by this architecture. The control of the reference divider accuracy and the comparator resolution is getting elusively difficult to achieve high resolution. Furthermore, the power consumption becomes prohibitively high. As a result, flash converters with more than 8b resolution are rare. Pipelined ADC Due to its complexity, the flash ADC is commonly used as coarse quantizers in the pipelined or multi-step ADCs rather than as a stand-alone ADC. For high resolution Bang-Sup Song 6 ECE163

above 12 bits, the complexity reaches about the maximum to handle. This leads us to pipeline larger number of sub-ranging blocks than 2. The pipelined ADC example shown in Fig. 6.9 is made of four 2b stages. V ref V ref V ref V ref 1 1 1 Residue 1 V IN 1 Residue 1 Residue 1 1 D out = 1 1 1 Fig. 6.9: Residue in 2b/stage pipelined ADC. Each stage resolves 2b like a 2b flash ADC, but it generates a residue voltage for the following stage. The residue voltage is the un-quantized portion of the signal that needs to be quantized in the subsequent pipelined stages. In this system, the complexity grows only linearly with the number of bits to resolve. Due to its simplicity, the pipeline ADC has been gaining popularity. In the ideal case, as the input is swept from to the full range V REF, the residue covers to V REF and also repeats every time reference voltage is subtracted. As the residue is pipelined, 2 bits are resolved in each stage, thereby making a total number of bits resolved be 8. Oversampling Σ ADC In recent years, high-resolution ADC/DAC at the low end of the spectrum such as for digital audio, voice, and instrumentation have been implemented using oversampling techniques. Oversampling can achieve high resolution by trading speed for accuracy, and reduce the effect of quantization noise and clock jitter. However, typical applications requiring a high-sampling rate can only allow Nyquist-rate sampling. The difference between plain pulse-code modulation (PCM) and Σ modulation is explained in Fig. 6.1. While the normal PCM coder (Nyquist-rate ADC) adds the quantization noise (Q) to the signal (X) to get the quantized (digitized) output Y, the Σ modulator modifies the quantization noise as shown in the first-order Σ modulator. The first-order modulator is simply a subtractor followed by an integrator. It is basically a quantized feedback system. So the quantization error inside the loop is reduced by the feedback loop gain. That is, the Q noise is reduced by 1/s, and the low-frequency gain of the integrator is f S /2πf BW (= M/π), where M is an oversampling ratio. Bang-Sup Song 7 ECE163

Nyquist ADC Σ ADC Q Q 1/s X Y X Y 1/s 1 Y = X + Q Y = X + Q 1 + 1/s 1 + 1/s ~ X + sq within f BW. Integrator gain f BW f S /2πf f S /2π Freq Fig. 6.1: Nyquist-rate vs. oversampling quantizer. Q X z -1 Y Fig. 6.: First-order Σ modulator model. The discrete-time model of a first-order Σ modulator is shown in Fig. 6.. The transfer function can be derived as follows. Y(z) =z 1 X(z) + (1 z 1 )Q(z) (6.7) Now assume that f N is the Nyquist sampling rate, and f S is the actual sampling frequency. Then, f S /f N is an oversampling ratio M. If f S >> f N, (1 z 1 ) is approximated as j2π(f/f S ). Therefore, the inband quantization noise after noise shaped can be obtained. Inband Noise = f N / 2 f N / 2 q 2 f S (2π) 2 (f /f S ) 2 df = q2 3 π 2 (f N /f S ) 3 (6.8) This implies that the quantization noise suppressed by 9dB per every 2 times oversampling. Note that just oversampling reduces the in-band quantization noise by 3dB, but an extra 6dB suppression results from the feedback. Bang-Sup Song 8 ECE163

The problem of the first-order modulator is its fixed pattern noise. For example, if the input X is a constant.25 for the normalized input range of 1, the output digital bit stream Y from a 1b first-order modulator will be 1 That is, the density of 1 is about 25% of the total, and this digital bit stream has a strong tone due to the fixed pattern of 1. This is why it is called pulse-density modulation too. Average pulse density represents the input. Higher-order modulators are commonly used to avoid this fixed pattern noise. Shown in Fig. 6.12 is the second-order modulator, basically cascading two first-order modulators. Q X z -1 z -1 Y 2 Fig. 6.12: Second-order Σ modulator model. This second-order modulator has a transfer function shaping the quantization noise by s 2. Y(z) =z 2 X(z) + (1 z 1 ) 2 Q(z) (6.9) Assuming the same for the first-order modulator, we can get the following. Inband Noise = f N / 2 f N / 2 q 2 f S (2π) 4 (f /f S ) 4 df = q2 5 π 4 (f N /f S ) 5 (6.1) Note that the in-band quantization noise is now suppressed by 15dB per every 2 times oversampling, and the fixed pattern noise prominent in the first-order modulator is reduced. 2 16 16 gain (db) Gain (db) Magfs (, NTF) Magfs (, NTF2) 1 1 2 L=1 L=2 SQNR (db) sqnr1( osr) sqnr2( osr) sqnr3( osr) 14 12 1 8 6 L=3 L=2 L=1 3 4 4.1.2.3.4.5 fs frequency (fs) Frequency (f S ) 2 2 1 1 1. 1 3 M 1 osr Fig. 6.13: Noise transfer function and SQNR vs. modulator order. 1 Bang-Sup Song 9 ECE163

The noise shaping functions of the first-order and second-order modulators are compared in Fig. 6.13, where L is the order of modulator. The second-order case suppresses the quantization noise more sharply at low frequencies. The signal-toquantization noise ratio (SQNR) is also shown for different-order modulators as a function of the over-sampling ratio M. DynamicRange = 3 2 2L +1 π 2L M 2L +1 (K 1) 2 (6.) where K is the number of quantization levels. That is, the quantization step is reduced from to /(K 1) for multi-level quantizers. As QSNR increases at 9dB and 15dB per 2 times oversampling, respectively, the effective number of bits can be estimated for firstorder and second-order modulators. ENOB =1.5Log 2 M.86 (Bits) forl=1 = 2.5Log 2 M 2.14 (Bits) forl = 2 (6.12) For example, if a single-bit ADC is placed inside 256-times over-sampled feedback loop, achievable number of bits are about and 17.8b using first-order and second-order modulators, respectively. t t rms = sin2πf BW t V 1 2 2πf BW 2 N 3 Worst-Case RMS Jitter 1n 1n 1p Jitter 1p (sec) 1p 1f 1kS/s 1MS/s 1MS/s 1MS/s 1f 8 1 12 14 16 Number of bits Fig. 6.14: Jitter effect on ADC resolution. Jitter Jitter is timing uncertainty in sampling. The right signal sampled at a wrong time is no different from the wrong signal sampled at a right time. As shown in Fig. 6.14, sampling error is highest at the zero-crossings at the highest input frequency. This sampling error due to the RMS jitter of t rms is small, and the RMS sampled error can be estimated for the worst case. V = sin2πbw t rms ~ 2πBW t rms (6.13) Since this RMS error should be smaller than the quantization noise Q, the worst case RMS timing jitter is estimated at different sampling rates. Bang-Sup Song 1 ECE163

φ 2d C I V REF -V REF X+ φ 1d C S φ 2 φ1 φ 1 Y+ X- V ic φ 1 φ 2 φ 1d φ 1 C S Y- φ 2d C I φ 2d -V REF V REF Fig. 6.15: First-order differential switched-capacitor Σ modulator. Implementation of Integrator The first-order modulator implemented differentially using switched-capacitor circuit is shown in Fig. 6.15. Both integrator and 1b comparator sample their inputs at φ 1. During φ 2, the integrator integrates, and the comparator latches to output either digital 1 or. This digital bit decides whether V REF is subtracted from or added to the input. When X=.25, V REF =1, and the latch threshold is set to.5, the output bit and the integrated output of the first-order modulator are as follows. Y 1 1 Σ(X-Y).25.5.75.25.5 Since it is the pulse density modulation, the average of the digital output bit-stream is.25, which is close to the input X. C v i R + v o 1/RC C I v i C S f S + v o f S C S /C I Fig. 6.16: Continuous-time and discrete-time integrators. Bang-Sup Song ECE163

Continuous-time and discrete-time integrators are compared in Fig. 6.16. To make the same integrator using the continuous-time RC integrator, the RC values should be chosen so that the following relation can be met if C S =C I. 1 RC = f S (6.14) Note the difference in units (rad/sec and Hz) in handling frequencies. Integrator Overload The unity-gain frequency of the integrator is set to be f S /2π (Hz). However, in the single-bit case, the large quantization noise is integrated by the integrator, and the signal plus this filtered quantization noise can exceed the signal range V REF if the signal is large. If the quantizer gain is less than 1, this feedback loop becomes nonlinear, and the system becomes unstable. To avoid this situation, it is common for designers to scale the integrator gain by half so that the signal plus the filtered quantization noise at the quantizer input can be contained below the level of V REF. It is the common-node scaling practice found in all active filter implementations. Although integrators are scaled, integrators in most oversampling modulators still get saturated, and the maximum peak signal is limited to be typically -3 to -6dB lower than the full range. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Lab #6 >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Consider a first-order continuous-time oversampling Σ modulator, and observe the over-sampling effect. Since it is a quantized feedback system, you need to clock the comparator output using a latch. The output of the latch is either digital high (ONE) or digital low (ZERO). These digital high and low voltages depend on your system bias. Use +/-2.5V for the supply voltage of the comparator and latch, but use +/-12V for the opamp. The latch works as a 1b DAC with a reference voltage of +/-2.5V. You can use LM3 as a comparator and CD413 as a latch. The CMOS D flip-flop CD413 can be used as a 1b comparator/latch without LM3, but you are free to use LM3. If the exact parts are not available, use available replacement parts. You should estimate the opamp slew rate requirement before you build the integrator. Note that this system is unstable for large signals. So try to scale the integrator gain by half either sizing the integrator capacitor or resistor larger by two. This will in effect lower the oversampling rate by 1/2. Even after integrator gain scaling, the modulator cannot operate with full-scale signals. Apply the maximum signal of half the magnitude, which is -6dB of the full scale. Bang-Sup Song 12 ECE163

1. Operate a 1b quantizer at 64kHz. If the oversampling ratio is 128, the Nyquist sampling rate is 5kHz. That is, your signal bandwidth is 2.5kHz. Set the integrator RC time constant to match the discrete-time integrator unity-gain time constant. Note that the resistor value should be set high enough so that the latch can drive it to the full swing of +/-2.5V. The latch output should be almost square wave changing its polarity with 64kHz clock. You should have a +/-2.5V digital bit-stream for feedback. If the latch cannot drive the resistor load, try an inverter or a buffer amplifier. Set also the inverting gain of unity for the input. 2. First estimate the dynamic range at an oversampling ratio of 128 by hand. Then simulate the modulator you designed using either SPICE or a math tool. Check whether your hand calculation matches with simulations. 3. Build a modulator, and measure the peak SNR at 128 times oversampling. The peak SNR should be about 6dB lower than the dynamic range. Your design and experimental result should be close with reasonable accuracy. If not, explain why. 4. Set the input voltage to 1V, V, and 1V, and record as many output bits in sequence. What do the percentages of ONE mean for these three cases? Bang-Sup Song 13 ECE163