GaN Power Switch & ALL-Switch TM Platform Application Notes AN01V650
Table of Contents 1. Introduction 3 2. VisIC GaN Switch Features 4 2.1 Safe Normally OFF circuit : 5 2.2 D-Mode GaN Transistor: 8 3. Reverse Recovery 10 4. Gate Driver Consideration 11 5. PCB Design: 14 5.1 Thermal Design 14 5.2 Thermal Interface Material (TIM): 16 5.3 Recommended Footprints 17 2/18
1. Introduction - The ever-growing market demand of vehicle electrification and energy harvesting, the global increase in information storage and processing and increase governmental regulation on energy efficiency put pressure on designers of power systems to increase the operational performance and power density of their products. VisIC Technologies has met these demands with the introduction of its proprietary High Voltage GaN Power Semiconductor Technology in combination with the developed ALL-Switch TM platform (Advanced Low Loss Switch). This document describes VisIC GaN power device characteristics in conjunction with its SMD package, and focus on applying this technology for high voltage, high power and high frequency applications. 3/18
2. VisIC GaN Switch Features To achieve the highest performance and reliability of the power transistor, VisIC has developed the ALL-Switch TM platform. The All-Switch TM is an SMT packaged MCM (multi chip module) featuring: Low inductance for high switching frequency Low switching losses (see Fig. 1) Safe normally OFF operation Low thermal resistance. Fig. 1 V80N65B Switching Energy 4/18
Products are available with top or bottom cooling versions: The ALL-Switch TM consists of three key technologies: - Enable Circuit: Si circuit providing a safe Normally OFF operation. - D-Mode GaN HEMT (High Electron Mobility Transistor) driven directly with proprietary design. - EMPACK: SMT package with embedded AlN substrate for electrical isolation and thermal conduction. 2.1 Safe Normally OFF circuit : Enable Circuit is incorporated in VisIC All-Switch TM platform beside the GaN transistor. Enable Circuit provides the switch with reliable and safe normally OFF function in case of driver or AUX PSU failure. Enable circuit performs two functions: Normally OFF (NOFF) Circuit. Under Voltage Lock Out (UVLO) Circuit. NOFF Circuit: This circuit is based on two low voltage P-Channel Si MOSFETS (Q2 and Q3), one fast Schottky diode D1 and pull-down resistor (see Fig. 2). It is responsible for the Normally OFF (NOFF) feature. 5/18
GaN Q1 NOFF Circuit Q3 D2 UVLO D1 Q4 Q2 Fig. 2 V80N65B internal schematic NOFF Circuit description of operation: This circuit operation has three cases 1) Only HV bias is applied to Drain Source -> as Q2 is normally OFF voltage rise on its Source, induces negative potential on the GaN gate throught Diode D1, which turns the GaN OFF (in a similar fashion to a Cascode operation). 2) HV bias is applied to Drain Source and a Driver is connected to Gate, VDD and GND pins (without AUX power)-> Q3 in its OFF state prevents high current path to the driver, and the scheme operates as in case 1. 6/18
3) During normal operation Q2 and Q3 are in ON state -> GaN is driven directly from driver, and conducts through turned ON Q2. UVLO Circuit: This circuit is based on a pre biased BJT (Q4) and 9V Zener diode (see Fig. 2). UVLO Circuit is provided to prevent erroneous operation during driver AUX PSU startup and shutdown or when VDD is below its specified operating circuits range. UVLO Circuit description of operation: The Zener senses the driver supply voltage, if the voltage is above 9V the BJT (Q4) is turned ON, which turns Q2 and Q3 ON allowing normal operation. If AUX power voltage drops below 9V the UVLO circuit, using the NOFF circuit, turns the GaN switch to normally OFF state. UVLO and NOFF features in VisIC product portfolio: V22N65A V80N65B V150N65B NOFF Internal Internal Internal UVLO External* Internal Internal *See section 4 for more detailed schematics. 7/18
2.2 D-Mode GaN Transistor: Structure: VisIC D-Mode GaN HEMT is a lateral device (see Fig. 3) Under-gate dielectric Source Gate Passivation GaN cap Drain AlGaN AlN Electron Flow 2DEG GaN Fig. 1 GaN HEMT structure Buffer layer Si substrate AlGaN/GaN hetero-epitaxy structure creates a channel of 2DEG (2- dimensional electron gas) which provides exceptional charge mobility and density. Characteristics: Fig. 3 GaN HEMT Structure The GaN transistor is rated for 650V blocking voltage D-Mode GaN is normally ON at 0V Gate Source bias the channel is fully open and conducts, at -7V Gate Source bias (threshold voltage) the channel closes and only small leakage current is present (Fig. 4). 8/18
Fig. 4 V80N65B GaN Output I/V Characteristics Reverse operation: As seen from the above graph (Fig. 4) during reverse Drain Source bias, channel conduction depends on the Gate Source voltage (Vgs) applied: At Vth < Vgs< 0V the channel exhibits bidirectional conductivity. Conduction loss equals Pcond=ISD 2 xrds(on),tj At Vgs < Vth (Vgs<-6V) the channel resistance exhibits diode like behavior, depanding on the negative Gate voltage bias. Conduction loss equals Pcond=ISDxVSD(at operated VGS) 9/18
3. Reverse Recovery The GaN transistor does not have a build-in body diode and in addition there is no reverse recovery charge due to its lateral structure. Despite of the absence of a body diode, the device is naturally capable of reverse conduction. The reverse conduction characteristics is a function of gate to drain bias. Since the GaN is capable of reverse conduction, it can be modelled as having a body diode. This body diode has higher forward voltage drop and no reverse recovery charge relative to Si. GaN HEMT Si MOSFET Qa=Qrr_diode Qb=Qoss Qrr=Qa+Qb Fig. 5 Recovered Charge - Si MOSFET vs. GaN HEMT As it can be seen in Fig. 5 MOSFET Qrr > GaN Qoss, therefore the losses on Si MOSFET are higher then on GaN HEMT. 10/18
4. Gate Driver Consideration In the ALL-Switch TM platform the GaN is driven directly, the following considerations should be taken into account when designing drive circuits. Recommended driver VDD voltage +12V ALL-Switch TM Gate pin is connected directly to driver output via gate resistor. V80N65B & V150N65B specifics: VisIC ALL-Switch TM GaN transistor Source ( VDD pin, Kelvin) is connected to driver VDD (see Fig. 6), as opposite to an N-Channel Si MOSFET where transistor Source is connected to Driver GND (see Fig. 7). Such connection allows to use standard 12V driver scheme to drive a D-mode GaN with negative Gate Source bias. GND pin is connected to driver GND. V80N65B D-Mode GaN Q1 Driver Fig. 6 V80N65B driving scheme 11/18
Driver Fig. 7 Standard N-Channel MOSFET driving scheme V22N65A specifics: As the UVLO circuit is external in this product the connection scheme is as follows (Fig. 8): V22N65A GaN Fig. 8 V22N65A driving scheme When the controller outputs an OFF signal, -12V is applied to GaN VGS, but relative to driver GND the voltage is 0V When the controller outputs an ON signal, 0V is applied to GaN VGS, but relative to driver GND the voltage is 12V 12/18
Driver AUX power supply isolation is required for the Enable circuitry, in both High and Low side of power applications (Fig. 9) Fig. 9 Driver AUX power supply connection for high and low side 13/18
Driver APPLICATION NOTES AN01V650 5. PCB Design: The ALL-Switch TM devices are intended for high speed, high frequency switching. To achieve the highest performance careful note should be taken to design the power and gate drive circuits. The gate drive loop from driver output to GaN and back to driver GND should be as short as possible to reduce parasitic inductance. Gate drive loop 5.1 Thermal Design in the EMPACK, a ceramic plate (AlN) is facilitating heat dissipation from the GaN die and to the PCB. For bottom cooling V80N65B thermal simulations show that RJC = 1.8[C/W]. There are two recommended PCB Thermal design. Copper coated Vias array. Copper inlay 14/18
Copper via design is well known and is widely used in the power semiconductor industry. Via arrays resistance can vary greatly, from 5[C/W] to 2[C/W], depending on the via array properties. VisIC-tech recommends the following for Via arrays: Via Plating Thickness Via diameter Plating Material Via Filling Via Area Via Pitch 1mil 3mil 0.2-0.4 Copper Not Filled 0.016 1-1.60 Copper Inlay provides the best overall performance but is more novel. VisIC suggests discussing the design with your PCB manufacturer. Below are the recommended Dimensions for a copper inlay inside a standard 1.6mm PCB. The Inlay s thickness should be the same as PCB thickness in order to ensure optimal heatsink attachment to PCB. Calculating the thermal resistance of the inlay RPCB is fairly simple using the following equation and the dimensions above( l-length, A-Area and K-Thermal Conductivity): R PCB = l A K = 1.6 26.73 0.389 = 0.15[ C W ] 15/18
5.2 Thermal Interface Material (TIM): VisIC recommends the use of a thermal paste material. There is no need for an Isolating TIM since the device thermal pad is isolated. Recommended Thermal Paste layer thickness: 0.1[mm]. Recommended Thermal Paste: MX-4. (K=8.5[W/MK) Approx. Theoretical Resistance: R TIM = 0.1 26.73 0.0085 =0.44[C/W] Please avoid applying a generous layer of Thermal paste, this only adds additional resistance. Thermal Paste should not be used to bridge particulary large air gaps between board to PCB. 16/18
5.3 Recommended Footprints IC land Pattern PCB pattern Metal Mask Opening Pattern Units W L P D H Wp Lp Pp Lm Wm X Em Pm mm 0.8 0.4 0.8 10 10 0.9 1.5 0.8 0.9 1.5 1.4 0.3 0.8 IC Package: PCB Pattern Metal Mask Do not trace over grayed out area 17/18
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