Comparson of V I c control wth Voltage Mode and Current Mode controls for hgh frequency (MHz) and very fast response applcatons P. Alou, J. A. Olver, V. Svkovc, 0. Garca and J. A. Cobos Abstract Hgh swtchng frequences (several MHz) allow the ntegraton of low power DC/DC converters. Although, n theory, a hgh swtchng frequency would make possble to mplement a conventonal Voltage Mode control (VMC) or Peak Current Mode control (PCMC) wth very hgh bandwdth, n practce, parastc effects and robustness lmts the applcablty of these control technques. Ths paper compares VMC and CMC technques wth the V Ic control. Ths control s based on two loops. The fast nternal loop has nformaton of the output capactor current and the error voltage, provdng fast dynamc response under load and voltage reference steps, whle the slow external voltage loop provdes accurate steady state regulaton. Ths paper shows the fast dynamc response of the V Ic control under load and output voltage reference steps and ts robustness operatng wth addtonal output capactors added by the customer. I. INTRODUCTION Nowadays, power supples for feedng mcroprocessors and portable devces demand fast dynamc response. An mportant dsadvantage of mplementng a lnear control s the need of a hgh bandwdth to acheve fast dynamc response. Ths hgh bandwdth s lmted ether by the swtchng frequency or by the robustness to component tolerances of the system. Well known non-lnear strateges are V 2 ([1], [2] and [3]) or hysteretc control of the output voltage [3]. Both requre sensng the output voltage rpple, whch s very small compared to the DC value and t s very senstve to parastc effects. It s also requred to have a trangular output rpple gven by a domnant ESR n the output capactor. The non-lnear and lnear control scheme proposed n [4] s based on a hysteretc control of the output capactor current of a Buck converter. It acheves a faster control acton under load steps snce the output capactor current reacts nstantaneously. The problem s to measure the output capactor current but t can be estmated wth the non-nvasve method descrbed n [5]. However, ths control technque suffers some lmtatons: varable frequency and hgh senstvty to current sensor msmatches. V 2 I C control proposed n [6] overcomes these lmtatons and provdes very fast response. It s based on the peak current mode control of the output capactor current that provdes very fast dynamc response under load steps, workng as a feedforward of the load current ([7], [8] and [9]). Informaton of the error between the reference voltage and the output voltage s added to the fast loop to acheve also very fast response under steps n the reference voltage. In ths paper, the V I c control s compared wth the conventonal Voltage Mode control (VMC) and Peak Current Mode control (PCMC) snce these control technques can provde very hgh bandwdth when the converter operates at very hgh frequency (several MHz). The comparson s focused on 1) response under load steps, 2) response under voltage steps, 3) output mpedance, 4) lne regulaton (response under nput voltage steps) and 5) robustness and stablty ssues when external capactors are added to the output. II. V 2 I C CONTROL: OPERATION PRINCIPLE The V I c control [6] s based on two loops, a fast nternal loop and a slow external loop (Fgure 1). It s called V I c control snce the output voltage s used n both fast and slow loops (V ) and the output capactor current ( c ) s also used n the fast loop. The control sgnal (Ctrl) obtaned n the fast loop s the addton of: 1) the estmaton of the output capactor current obtaned wth the smple and non-nvasve sensor descrbed n [5], 2) the error between the voltage reference (V ref ) and the output voltage (V out ) and 3) a compensatng slope. Ths control sgnal s compared wth the reference (Ref) obtaned n the slow external loop at the output of a voltage regulator. Ths work has been partally supported by Spansh Government Innovaton and Scence Offce (MCINN), under research grant no. DPI- 2010-20096, "FAST" project.
The modulator s a peak mode control and therefore a compensatng slope s needed to avod sub-harmonc oscllatons over 50% duty cycles. The compensatng slope not only avods sub-harmonc oscllatons, but also helps to desenstze ths technque to current sensor msmatches and parastc effects. On the other hand, ncreasng the compensatng slope, the dynamc response s reduced. Therefore, there s a trade-off between stablty and dynamc response. The man swtch s turned on every cycle, thanks to a RS latch, and turned off when the control sgnal reaches the reference (Fgure 2). Hence, ths control technque prevents from the problem of varable frequency. The output capactor current measurement provdes fast dynamc response to load transtons snce t behaves as a feed-forward of the load current and any change s nstantaneously reflected n the control sgnal (Ctrl). When a postve load step occurs, the output capactor current goes down almost mmedately and therefore the control sgnal goes down as well. The duty cycle can be even saturated untl the control sgnal reaches the reference agan. On the other hand, the output error voltage feedback mproves the dynamc response under changes n the output voltage reference as t s reflected n the control sgnal (Ctrl) and n the reference sgnal (Reí). Fnally, the external voltage loop provdes accurate steady state regulaton. The operaton of ths control technque s expermentally valdated on a buck converter beng V IN =3V, V 0 UT = 1V, f sw =lmhz, L=440nH and COUT = 4 ^F and the external voltage loop s desgned wth 10kHz bandwdth. The dynamc response of the V I c control under postve load step s shown n Fg. 3. The control reacts almost mmedately closng the man MOSFET. The nductance current follows the reference wth hgh slew rate. The recovery tme s only 3 us (three swtchng cycles). The expermental results obtaned under postve reference step are shown n Fg. 4. The voltage reference step s done from 0.9V to 1.9V. The control reacts almost nstantaneously needng only two swtchng cycles to reach the new operatng pont and then, the external voltage loop provdes the accurate steady state regulaton. In addton, there s no overshoot n the output voltage due to the transent response. III. COMPARISON OF THE PROPOSED CONTROL WITH VOLTAGE MODE AND PEAK CURRENT MODE CONTROL The control schemes that are compared n ths paper are Voltage Mode control (Fgure 5), Peak Current Mode Control (Fgure 6) and V I c control (Fgure 1). Slopped SmjIeSeo. 1HC» SIJUM01112M r ry f 1 T f Slow loop Modulator Load Fgure 3. Expermental results. Postve load step of 4A and 40A/us (2A/dv), nductor current I L (2A/dv), output voltage V 0 UT (500mV/dv) and gate sgnal (5V/dv) wth 2us/dv tme scale. Fgure 1. Proposed control technque: V I c control. B o a_! S Re '!. ' I':. Htf n n. un»j-h M n IMI n nn H > UDITp ínsatng S ope As ^ Ctrl t Fgure 2. Out Proposed control: operatng prncple. t.- -. r,.,.,.,.,.,.,...,... Fgure 4. Expermental results. Postve voltage reference step of IV and 20V/(s (500m/dv), nductor current I L (2A/dv), output voltage V 0 UT (500mV/dv) and gate sgnal (5V/dv) wth 2(s/dv tme scale.
Fgure 5. Voltage Mode Control (VMC) Fgure 6. Peak Current Mode Control (PCMC) These control technques are appled to a Synchronous Buck converter wth the followng specfcatons: Input voltage range: 4V - 5.5V, output voltage: 1.2V - 2.2V, output current: OA - 6A, swtchng frequency: 5MHz, output nductor: loonh and output capactor: IO^IF (ESR=2mQ, ESL=200pH). The three control technques have been modelled, desgned and smulated wth the smulaton tool SIMPLIS. It allows to do both transent analyss and small sgnal analyss of swtchng converters. The VMC and the PCMC have been desgned to have a voltage loop bandwdth of 500kHz. The reasons for 500kHz bandwdth are: It s one tenth of the swtchng frequency Robustness under addtonal output capactors: the hgher the bandwdth, the worse the stablty under external capactors added at the output. Robustness under parastc varatons: the resonance frequency of small ceramc capactors s around 1.5MHz-3MHz. Snce the loop gan s very senstve to ths resonance, the bandwdth should be far enough. A. Open Loop Gan In the V 2 I C control the selected bandwdth for the external voltage loop s 50 khz. It s 10 tmes smaller than the bandwdth of VMC and PCMC snce the dynamc response of ths control s provded by the fast loop. Fg. 7 shows the open loop gan (magntude and phase) for the three control technques. The loop s desgned for the nomnal output capactor (IO^IF). The phase margn s 70 n the three controls and the bandwdth s 50kHz n the V 2 I C control and 500kHz n the VMC and PCMC. B. Closed Loop Output Impedance Fg. 8 shows the correspondng closed loop output mpedance for these three control technques. It clearly shows that the V 2 I C control output mpedance s much lower up to 1.8MHz; the fast nternal loop of the V 2 I C control provdes a really fast response wth a 1.8MHz equvalent bandwdth, beng only 50kHz the bandwdth of the slow external loop (voltage loop). C. Dynamc Response The dynamc response of the V 2 I C control s much faster than VMC and PCMC. Under load steps (Fgure 9) the voltage devaton s 50mV whle t s twce hgher (loomv) n VMC or PCMC. Under reference voltage steps (Fgure 10) the dfferences among the three controls are mnor. V 2 I C control follows approprately the reference step (185mV overshoot, 12 xs settlng tme). The VMC follows also the step reference although t needs a hgher settlng tme (20JAS). The PCMC presents a hgher overshoot (360mV). D. Robustness: Extra Capactors added at the Output The V 2 I C control presents also very good performance under addton of extra capactors at the output of the converter. Typcally, the customer can add addtonal capactors between the converter and the load and the system should be robust enough to handle the unknown addtonal capactor wthout havng stablty problems. Fg. 11 shows the response of the three control technques under a load step when the capactor s 50 tmes hgher than de nomnal value. Fg. 12 shows the open loop gan of the three control technques when the capactor s 50 tmes hgher than de nomnal value. VMC has stablty problems, the phase margn s only 11 and the response under the load step s too oscllatng. PCMC s more robust to the capactor varaton but the bandwdth s too low (18kHz) and has a poor response under the load step, 65mV voltage devaton for such a bg output capactor (50 x 10^F). The V 2 I C control s very robust and keeps a stable behavor (39 phase margn) and a low voltage devaton (8mV) when the output capactor s 50 tmes hgher than the nomnal value. The low bandwdth of the external voltage loop and the compensaton slope provdes the robustness of the V 2 I C control. E. Lne Regulaton: Response under Input Voltage Steps Fg. 13 shows the output voltage response under a voltage step at the nput of the Buck converter. PCMC presents very good behavor snce t has nherent feed-forward of the nput voltage. V 2 I C control also presents very good response thanks to the fast nternal loop. Fnally, VMC presents a poor behavor under lne steps.
Peak current mode control V 2^ con tro AB=50kHz OdB ~^- :::: =,-. r 0- * IX WO 500 Ik 2k 5k Ik 20k _...,, AB=50kHz ^^^ ^-~-. HTr^. "-«s. ^\ )k 200k. ( 2W 5*1 I0M \B=500kHz Fgure 7. Open loop gan wth the nomnal output capactor 10 F: Magntude and phase 2D Peakcurr entro ode control AI -500 khz^_-~~~ AB-5001 thz Vlr cont rol AB=50k Hz 1 Equvalent V Z I C control khz bandwdth frv n T = 50nW n I 1.8MHz DC- 3C- 60-10- *"- -5s H^^ v ^4- ^H- ^r- ^ 80- n 1» 200 S k 2k 1 k 20k S h 1C 0k 200k 5C 0k 1 M 2M 5 ñ 10M Fgure 8. Closed loop output mpedance (20dB/dv) wth the nomnal output capactor 10 F Fgure 9. Output voltage response under a 4A load step wth the nomnal output capactor 10 F (20mV/dv, 10 s/dv E <0 m r > 3 E // 12 a It \ / 185 mv H» 2C IS =eak current r node control \B=500kHz V! lr CO ntrol AB=5 khz Voltage mo e control AB=50 0kHz! V 2 I C cont rol 0kHz band wdth ^ AV 0UT = a mv / Peak cu rrent mode control khz banclu dth soo A V 0UT = 65m V s*" Voltage m )de contro 51 )0kHz banc wdth NO STABLE nun tnr-'t fet Fgure 10. Reference voltage step: output voltage (0.2V/dv) when the reference voltage steps from 1.2V to 2.2V wth the nomnal output capactor 10 F (5us/dv) Fgure 11. Output voltage response under a 4A load step beng the output capactor 50 x 10^F (20mV/dv, lo^s/dv)
Peak current mode control V 2 I C contro AB=50kHz C out =10MF I 20m\ \ Udb ^=~T ==1 *~^ ' 1 1 1 1 *^ Peak current mode control ICO 6D 10 200 51 0 k 2k A 1 1 ^K T>. ^r^^- P ^^'C! Tp =r " " ^ ^"*"^- 1 AE =68kH*---, ' ÁB=18k 2 fzab=akhz" X ' 1 ** '"" " " ' Vlc control \B=50kHz Fgure 12. Open loop gan wth an output capactor 50 x lo^f: Magntude and phase Fgure 13. Lne regulaton: output voltage when the nput voltage steps from 4V to 5.5V wth the nomnal output capactor lo^f Tek Run: 50.0MS/S sample loomv. Duty cycle s almost saturated durng two cycles, ncreasng rapdly the current through the nductor and then the duty cycle s lowered to smoothly reduce the nductor current. Fgure 14. Expermental results: reference voltage step from 0.8V to 1.4V. Output voltage (200mV/dv), estmated capactor current (2A/dv), nductor current (2A/dv) and tme scale lus/dv. IV. EXPERIMENTAL RESULTS A 5MHz Buck converter has been developed to valdate the behavor of the V 2 I C control. The prototype has been desgned for the same specfcatons shown n secton III. Fg. 14 shows the response of the V I c control when the voltage reference steps from 0.8V up to 1.4V. The voltage step s approprately followed, beng the voltage overshoot about V. CONCLUSIONS The V I c control, based on two loops, a fast nternal loop and a slow external loop, s very approprate for hgh swtchng frequency converters. The low bandwdth of the external voltage loop together wth the compensatng slope provde a large robustness to ths control. Ths control s presented and valdated n [6]. In ths paper, the V I c control s compared wth a hgh bandwdth Voltage Mode Control (VMC) and a hgh bandwdth Peak Current Mode Control (PCMC) for a 5MHz Buck converter. The comparson s done based on the SIMPLIS smulaton tool. The three control technques have been modeled, desgned and smulated based on ths tool. The results of the comparson are summarzed n the followng table (Table I). The man concluson of ths paper s that the V 2 I C control, compared wth VMC and PCMC, presents the fastest dynamc response as well as the best robustness to deal wth addtonal output capactors that the user can put between the load and the converter. TABLE I. SUMMARY OF THE COMPARISON VMC 500kHz bandwdth PCMC 500kHz bandwdth V2IC control 50kHz bandwdth Dynamc response under load steps Fast response Fast response Very fast response Dynamc response under reference voltage steps Approprate trackng (longer settlng tme) Poor trackng (hghest overshoot) Approprate trackng Robustness under addtonal C0UT (x50 tmes) UNSTABLE 11 phase margn Stable but poor response Stable and fast response Closed loop Output mpedance Medum Hghest Lowest (1.8MHz equvalent bandwdth) Lne regulaton: Input voltage step Worst response Best response Very good response
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