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Typical Applications l Industrial Motor Drive Benefits l Advanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free Description This Advanced Planar Stripe HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low onresistance per silicon area. Additional features of this HEXFET power MOSFET are a 75 C junction operating temperature, low RθJC, fast switching speed and improved repetitive avalanche rating. This combination makes the design an extremely efficient and reliable choice for use in a wide variety of applications. G HEXFET Power MOSFET D S PD - 94972A V DSS = 75V R DS(on) = 0.007Ω I D = 40A TO-220AB Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 40 I D @ T C = C Continuous Drain Current, V GS @ 0V 97 A I DM Pulsed Drain Current 550 P D @T C = 25 C Power Dissipation 330 W Linear Derating Factor 2.2 W/ C V GS Gate-to-Source Voltage ± 20 V E AS Single Pulse Avalanche Energy 430 mj I AR Avalanche Current 82 A E AR Repetitive Avalanche Energy See Fig.2a, 2b, 5, 6 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.5 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Mounting Torque, 6-32 or M3 screw 0 lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.45 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 HEXFET(R) is a registered trademark of International Rectifier. www.irf.com 07/23/0

Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 75 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.086 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 5.9 7.0 mω V GS = 0V, I D = 82A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = 0V, I D = 250µA g fs Forward Transconductance S V DS = 25V, I D = 82A I DSS Drain-to-Source Leakage Current 20 V µa DS = 75V, V GS = 0V 250 V DS = 60V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 200 V GS = 20V na Gate-to-Source Reverse Leakage -200 V GS = -20V Q g Total Gate Charge 50 220 I D = 82A Q gs Gate-to-Source Charge 3 47 nc V DS = 60V Q gd Gate-to-Drain ("Miller") Charge 50 76 V GS = 0V t d(on) Turn-On Delay Time 6 V DD = 38V t r Rise Time 40 I D = 82A ns t d(off) Turn-Off Delay Time 68 R G = 2.5Ω t f Fall Time 20 V GS = 0V Between lead, D L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 530 V GS = 0V C oss Output Capacitance 890 pf V DS = 25V C rss Reverse Transfer Capacitance 30 ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 600 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 570 V GS = 0V, V DS = 60V, ƒ =.0MHz C oss eff. Effective Output Capacitance 40 V GS = 0V, V DS = 0V to 60V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 40 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 550 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 82A, V GS = 0V t rr Reverse Recovery Time 93 40 ns T J = 25 C, I F = 82A Q rr Reverse RecoveryCharge 340 50 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Starting T J = 25 C, L = 0.30mH R G = 25Ω, I AS = 82A. (See Figure 2). ƒ I SD 82A, di/dt 30A/µs, V DD V (BR)DSS, T J 75 C Pulse width 400µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. 2 www.irf.com

I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) 0 0 TOP BOTTOM VGS 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V I D, Drain-to-Source Current (A) 0 0 TOP BOTTOM VGS 5V 0V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0.00 3.0 I D = 37A.00 T J = 25 C 0.00 T J = 75 C V DS = 5V 20µs PULSE WIDTH.0 3.0 5.0 7.0 9.0.0 3.0 5.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 2.0.5.0 0.5 V GS = 0V 0.0-60 -40-20 0 20 40 60 80 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3

C, Capacitance(pF) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds C rss = C gd C oss = C ds C gd SHORTED 2 0 I D = 82A V DS = 60V V DS = 37V V DS = 5V 00 0 Ciss Coss V GS, Gate-to-Source Voltage (V) 8 6 4 2 Crss 0 V DS, Drain-to-Source Voltage (V) 0 0 40 80 20 60 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0.00 00.00 T J = 75 C 0 OPERATION IN THIS AREA LIMITED BY R DS (on) 0.00 T J = 25 C µsec.00 V GS = 0V 0.0 0.0 0.5.0.5 2.0 V SD, Source-toDrain Voltage (V) 0 Tc = 25 C Tj = 75 C Single Pulse msec 0msec 0 0 V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com

40 LIMITED BY PACKAGE V DS R D 20 R G V GS D.U.T. - V DD I D, Drain Current (A) 80 60 40 0V Pulse Width µs Duty Factor 0. % Fig 0a. Switching Time Test Circuit 20 0 25 50 75 25 50 75 T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% 0% V GS t d(on) t r t d(off) t f Fig 0b. Switching Time Waveforms Thermal Response (Z thjc ) 0. 0.0 D = 0.50 0.20 0.0 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) P DM t t 2 Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc T C 0.00 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5

V GS(th) Gate threshold Voltage (V) 5V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) 800 640 480 320 60 TOP BOTTOM 0 25 50 75 25 50 Starting Tj, Junction Temperature ( C) I D 34A 58A 82A I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current 0 V Q GS Q GD 3.5 V G 3.0 Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform 2.5 2.0 I D = 250µA 2V.2µF 50KΩ.3µF.5 V GS D.U.T. V - DS.0-75 -50-25 0 25 50 75 25 50 75 200 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage Vs. Temperature 6 www.irf.com

E AR, Avalanche Energy (mj) Avalanche Current (A) 0 Duty Cycle = Single Pulse 0.0 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses 0.05 0 0.0.0E-07.0E-06.0E-05.0E-04.0E-03.0E-02.0E-0 tav (sec) Fig 5. Typical Avalanche Current Vs.Pulsewidth 500 400 300 200 0 TOP Single Pulse BOTTOM 0% Duty Cycle I D = 40A 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av Fig 6. Maximum Avalanche Energy Vs. Temperature www.irf.com 7

Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =0V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 7. For N-channel HEXFET power MOSFETs 8 www.irf.com

TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF00 LOT CODE 789 ASSEMBLED ON WW 9, 2000 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead - F ree" INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 9 LINE C TO-220AB package is not recommended for Surface Mount Application Notes:. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) 252-705 TAC Fax: (30) 252-7903 Visit us at www.irf.com for sales contact information.07/200 www.irf.com 9