Improved Second Source to the EL ADEL FEATURES Ideal for Video Applications.% Differential Gain. Differential Phase. db Bandwidth to 5 MHz (G = +) High Speed 9 MHz Bandwidth ( db) 5 V/ s Slew Rate ns Settling Time to.% (V O = V Step) Low Noise.9 nv/ Hz Input Voltage Noise Low Power.8 ma Supply Current. ma Supply Current (Power-Down Mode) High Performance Disable Function Turn-Off Time of ns Input to Output Isolation of 5 db (Off State) GENERAL DESCRIPTION The ADEL is an improved second source to the EL. This op amp improves on all the key dynamic specifications while offering lower power and lower cost. The ADEL offers 5% more bandwidth and gain flatness of. db to beyond 5 MHz. In addition, differential gain and phase are less than.5% and.5 while driving one back terminated cable (5 Ω). NORMALIZED db +.. +.. R L = 5 R L = k 5V 5V BAL IN +IN V 8-Lead PDIP (N) 8 ADEL 5 TOP VIEW CONNECTION DIAGRAMS DISABLE V+ OUTPUT BAL -Lead SOIC (R) NC NC BAL ADEL 9 DISABLE NC TOP VIEW 8 NC IN V+ NC 5 NC +IN 5 OUTPUT NC NC V 8 BAL NC 9 NC NC NC NC = NO CONNECT The ADEL offers other significant improvements. The most important is lower power supply current (% less than the competition) with higher output drive. Important specifications like voltage noise and offset voltage are less than half of those for the EL. The ADEL also provides an improved disable feature. The disable time (to high output impedance) is ns with guaranteed break before make. The ADEL is offered for the industrial temperature range of C to +85 C and comes in both PDIP and SOIC packages. DIFFERENTIAL %..9.8...5... = + R F = 5 R L = 5 f C =.58MHz IRE MODULATED RAMP..8.....8.. DIFFERENTIAL Degrees.. k M M M FREQUENCY Hz Figure. Fine-Scale Gain (Normalized) vs. Frequency for Various Supply Voltages, R F = 5 Ω, Gain = + 5 8 9 5 SUPPLY VOLTAGE V Figure. Differential Gain and Phase vs. Supply Voltage Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 8/9- www.analog.com Fax: 8/-8 Analog Devices, Inc. All rights reserved.
ADEL SPECIFICATIONS ADELA Parameter Conditions Temperature Min Typ Max Unit INPUT OFFSET VOLTAGE.5.5 mv T MIN to T MAX.. mv Offset Voltage Drift µv/ C COMMON-MODE REJECTION V CM = ± V V OS T MIN to T MAX 5 db ±Input Current T MIN to T MAX.. µa/v POWER SUPPLY REJECTION V S = ±.5 V to ±8 V V OS T MIN to T MAX 5 db ±Input Current T MIN to T MAX.5.5 µa/v INPUT BIAS CURRENT Input T MIN to T MAX.5.5 µa +Input T MIN to T MAX 5 µa INPUT CHARACTERISTICS +Input Resistance MΩ Input Resistance Ω +Input Capacitance pf OPEN-LOOP TRANSRESISTANCE V O = ± V R L = Ω T MIN to T MAX.5 MΩ OPEN-LOOP DC VOLTAGE R L = Ω, V OUT = ± V T MIN to T MAX 8 db R L = Ω, V OUT = ±.5 V T MIN to T MAX 88 db OUTPUT VOLTAGE SWING R L = Ω T MIN to T MAX ±. ±. V Short-Circuit Current 5 ma Output Current T MIN to T MAX ma POWER SUPPLY Operating Range ±. ±8 V Quiescent Current T MIN to T MAX.8. ma Power-Down Current T MIN to T MAX.. ma Disable Pin Current Disable Pin = V T MIN to T MAX 9 µa Min Disable Pin Current to Disable T MIN to T MAX µa DYNAMIC PERFORMANCE db Bandwidth G = +; R FB = 8 9 MHz G = +; R FB = 5 MHz G = +; R FB = 8 MHz. db Bandwidth G = +; R FB = 5 5 MHz Full Power Bandwidth V O = V p-p, R L = Ω 8 MHz Slew Rate R L = Ω, G = + 5 V/µs Settling Time to.% V Step, G = ns Differential Gain f =.58 MHz. % Differential Phase f =.58 MHz. Degree INPUT VOLTAGE NOISE f = khz.9 nv/ Hz INPUT CURRENT NOISE I IN, f = khz pa/ Hz +I IN, f = khz.5 pa/ Hz OUTPUT RESISTANCE Open Loop (5 MHz) 5 Ω Specifications subject to change without notice. (@ T A = 5 C, V S = 5 V dc, R L = 5 Ω, unless otherwise noted.)
ADEL ABSOLUTE MAXIMUM RATINGS Supply Voltage................................ ±8 V Internal Power Dissipation....... Observe Derating Curves Output Short Circuit Duration.... Observe Derating Curves Common-Mode Input Voltage..................... ±V S Differential Input Voltage........................ ± V Storage Temperature Range PDIP and SOIC..................... 5 C to +5 C Operating Temperature Range........... C to +85 C Lead Temperature Range (Soldering sec)......... C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8-Lead PDIP: θ JA = 9 C/W -Lead SOIC Package: θ JA = 5 C/W. F ADEL + +V S V S k 5. F Figure. Offset Null Configuration MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the ADEL is limited by the associated rise in junction temperature. For the plastic packages, the maximum safe junction temperature is 5 C. If the maximum is exceeded momentarily, proper circuit operation will be restored as soon as the die temperature is reduced. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves in figure. While the ADEL is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. TOTAL POWER DISSIPATION W....8.....8. 8-LEAD PDIP -LEAD SOIC. 8 AMBIENT TEMPERATURE C Figure. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Temperature Package Package Model Range Description Option ADELAN C to +85 C 8-Lead PDIP N-8 ADELAR- C to +85 C -Lead SOIC R- ADELAR--REEL C to +85 C -Lead SOIC R- CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADEL features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ADEL Typical Performance Characteristics = + R L = 5 = + R L = k CLOSED-LOOP db 9 5 8 5 SHIFT Degrees CLOSED-LOOP db 9 5 8 5 SHIFT Degrees 5 TPC. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = 5 Ω, R F = kω for ±5 V, 9 Ω for ±5 V 5 TPC. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = kω, R F = kω for ±5 V, 9 Ω for ±5 V db BANDWIDTH MHz 9 8 5 = + R L = 5 V O = 5mV p-p R F = 5 R F = k PEAKING <.db PEAKING <.db db BANDWIDTH MHz 9 8 5 = R L = 5 V O = 5mV p-p R F = 99 R F = 8 PEAKING <.db PEAKING <.db R F =.5k R F = k 8 8 SUPPLY VOLTAGE V TPC. db Bandwidth vs. Supply Voltage, Gain = +, R L = 5 Ω 8 8 SUPPLY VOLTAGE V TPC 5. db Bandwidth vs. Supply Voltage, Gain =, R L = 5 Ω = R L = 5 8 = R L = k 8 CLOSED-LOOP db 5 9 5 SHIFT Degrees CLOSED-LOOP db 5 9 5 SHIFT Degrees 5 TPC. Closed-Loop Gain and Phase vs. Frequency, G =, R L = 5 Ω, R F = 8 Ω for ±5 V, Ω for ±5 V 5 TPC. Closed-Loop Gain and Phase vs. Frequency, G =, R L = kω, R F = 8 Ω for V S = ±5 V, Ω for ±5 V
ADEL = + R L = 5 = + R L = k CLOSED-LOOP db 5 9 5 8 5 SHIFT Degrees CLOSED-LOOP db 5 9 5 8 5 SHIFT Degrees TPC. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = 5 Ω, R F = 5 Ω for ±5 V, 5 Ω for ±5 V TPC. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = kω, R F = 5 Ω for ±5 V, 5 Ω for ±5 V db BANDWIDTH MHz 9 8 5 = + R L = 5 V O = 5mV p-p PEAKING <.db R F = 5 R F = 5 PEAKING <.db R F = k db BANDWIDTH MHz 9 8 5 = + R L = 5 V O = 5mV p-p R F = R F = R F = k PEAKING <.5dB PEAKING <.db 8 8 SUPPLY VOLTAGE V TPC 8. db Bandwidth vs. Supply Voltage, Gain = +, R L = 5 Ω 8 8 SUPPLY VOLTAGE V TPC. db Bandwidth vs. Supply Voltage, Gain = +, R L = 5 Ω CLOSED-LOOP db 9 8 = + R F = R L = 5 9 5 8 5 SHIFT Degrees CLOSED-LOOP db 9 8 = + R F = R L = k 9 5 8 5 SHIFT Degrees 5 TPC 9. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = 5 kω 5 TPC. Closed-Loop Gain and Phase vs. Frequency, G = +, R L = kω 5
ADEL OUTPUT VOLTAGE V p-p 5 5 5 OUTPUT LEVEL FOR % THD V S = CLOSED-LOOP OUTPUT RESISTANCE. = + R F = 5 V S = k M M FREQUENCY Hz M. k k M FREQUENCY Hz M M TPC. Maximum Undistorted Output Voltage vs. Frequency TPC. Closed-Loop Output Resistance vs. Frequency POWER SUPPLY REJECTION db 8 5 R F = 5 A V = + V S = CURVES ARE FOR WORST-CASE CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS HELD CONSTANT SUPPLY CURRENT ma 9 8 5 V S = k k M FREQUENCY Hz M M 8 JUNCTION TEMPERATURE C TPC. Power Supply Rejection vs. Frequency TPC. Supply Current vs. Junction Temperature V S = TO 5V R L = VOLTAGE NOISE nv/ Hz INVERTING INPUT CURRENT VOLTAGE NOISE NONINVERTING INPUT CURRENT CURRENT NOISE pa/ Hz SLEW RATE V/ s 9 8 5 = = + = + k k k FREQUENCY Hz TPC 5. Input Voltage and Current Noise vs. Frequency 8 8 SUPPLY VOLTAGE V TPC 8. Slew Rate vs. Supply Voltage
ADEL k 5 +V S. F +V S. F 5 ADEL V O ADEL V O V IN R T +. F R L V IN R T +. F R L V S V S Figure 5. Connection Diagram for A VCL = + 8 +V S. F Figure. Connection Diagram for A VCL = + +V S. F V IN 8 ADEL V O ADEL V O +. F R L V IN R T +. F R L V S V S Figure. Connection Diagram for A VCL = Figure 8. Connection Diagram for A VCL = +
ADEL GENERAL DESIGN CONSIDERATIONS The ADEL is a current feedback amplifier optimized for use in high performance video and data acquisition systems. Since it uses a current feedback architecture, its closed-loop bandwidth depends on the value of the feedback resistor. The db bandwidth is also somewhat dependent on the power supply voltage. Lowering the supplies increases the values of internal capacitances, reducing the bandwidth. To compensate for this, smaller values of feedback resistors are used at lower supply voltages. POWER SUPPLY BYPASSING Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can contribute to resonant circuits that produce peaking in the amplifier s response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than µf) will be required to provide the best settling time and lowest distortion. Although the recommended. µf power supply bypass capacitors will be sufficient in most applications, more elaborate bypassing (such as using two paralleled capacitors) may be required in some cases. CAPACITIVE LOADS When used with the appropriate feedback resistor, the ADEL can drive capacitive loads exceeding pf directly without oscillation. Another method of compensating for large load capacitance is to insert a resistor in series with the loop output. In most cases, less than 5 Ω is all that is needed to achieve an extremely flat gain response. OFFSET NULLING A kω pot connected between Pins and 5, with its wiper connected to V+, can be used to trim out the inverting input current (with about ± µa of range). For closed-loop gains above about 5, this may not be sufficient to trim the output offset voltage to zero. Tie the pot s wiper to ground through a large value resistor (5 kω for ±5 V supplies, 5 kω for ±5 V supplies) to trim the output to zero at high closed-loop gains. DISABLE MODE By pulling the voltage on Pin 8 to common ( V), the ADEL can be put into a disabled state. In this condition, the supply current drops to less than.8 ma, the output becomes a high impedance, and there is a high level of isolation from input to output. In the case of a line driver, for example, the output impedance will be about the same as that for a.5 kω resistor (the feedback plus gain resistors) in parallel with a pf capacitor (due to the output), and the input to output isolation will be better than 5 db at MHz. Leaving the disable pin disconnected (floating) will leave the part in the enabled state. In cases where the amplifier is driving a high impedance load, the input to output isolation will decrease significantly if the input signal is greater than about. V p p. The isolation can be restored to the 5 db level by adding a dummy load (say 5 Ω) at the amplifier output. This will attenuate the feedthrough signal. (This is not an issue for multiplexer applications where the outputs of multiple ADELs are tied together as long as at least one channel is in the ON state.) The input impedance of the disable pin is about 5 kω in parallel with a few pf. When grounded, about 5 µa flows out of the disable pin for ±5 V supplies. Break-before-make operation is guaranteed by design. If driven by standard CMOS logic, the disable time (until the output is high impedance) is about ns and the enable time (to low impedance output) is about ns. Since it has an internal pullup resistor of about 5 kω, the ADEL can be used with open drain logic as well. In that case, the enable time increases to about µs. If there is a nonzero voltage present on the amplifier s output at the time it is switched to the disabled state, some additional decay time will be required for the output voltage to relax to zero. The total time for the output to go to zero will normally be about 5 ns; it is somewhat dependent on the load impedance. OPERATION AS A VIDEO LINE DRIVER The ADEL is designed to offer outstanding performance at closed-loop gains of or greater. At a gain of, the ADEL makes an excellent video line driver. The low differential gain and phase errors and wide. db bandwidth are nearly independent of supply voltage and load. For applications requiring widest. db bandwidth, it is recommended to use 5 Ω feedback and gain resistors. This will result in about.5 db of peaking and a. db bandwidth of MHz on ±5 V supplies. 8
ADEL OUTLINE DIMENSIONS 8-Lead Plastic Dual-in-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters).5 (9.5).5 (9.).55 (9.).8 (.5) MAX 8 5.95 (.9).85 (.).5 (.98). (.5) BSC.5 (.8) MIN.5 (.8). (.) SEATING PLANE. (.9). (.5). (.5).5 (.).8 (.).5 (.). (.).5 (8.). (.8). (.).5 (.8).5 (.). (.5).5 (.8). (.5).8 (.) COMPLIANT TO JEDEC STANDARDS MO-95AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN -Lead Standared Small Outline Pacakge [SOIC] Wide Body (R-) Dimensions shown in millimeters and (inches). (.58). (.9). (.99). (.9).5 (.9). (.9). (.8). (.9).5 (.).5 (.95).5 (.95) 5.5 (.98) COPLANARITY.. (.5) BSC.5 (.). (.) SEATING PLANE. (.). (.9) 8. (.5). (.5) COMPLIANT TO JEDEC STANDARDS MS-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 9
ADEL Revision History Location Page / Data Sheet changed from REV. to. Format updated...................................................................................universal 8-Lead PDIP (N) and -Lead SOIC (R) updated........................................................universal OUTLINE DIMENSIONS updated......................................................................... 9
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