FEATURES Low supply current: 25 µa max Very low input bias current: pa max Low offset voltage: 75 µv max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±3 V Rail-to-rail output Unity-gain stable No phase reversal SC7 package Low Power, Rail-to-Rail Output Precision JFET Amplifier AD864/AD8642/AD8643 APPLICATIONS NC = NO CONNECT Line-/battery-powered instruments Figure 2. 8-Lead SOIC (R-8) Photodiode amplifiers OUT A 8 V+ Precision current sensing IN A AD8642 2 7 OUT B Medical instrumentation +IN A 3 6 TOP VIEW IN B Industrial controls V 4 (Not to Scale) 5 +IN B Precision filters Portable audio Figure 3. 8-Lead SOIC (R-8) ATE OUT A 8 V+ IN A 2 AD8642 7 OUT B TOP VIEW +IN A 3 6 IN B GENERAL DESCRIPTION (Not to Scale) The AD864/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. The outputs remain stable with capacitive loads of more than 5 pf. The AD864/AD8642/AD8643 are suitable for applications utilizing multichannel boards that require low power to manage heat. Other applications include photodiodes, ATE reference level drivers, battery management, and industrial controls. The AD864/AD8642/AD8643 are fully specified over the extended industrial temperature range of 4 C to +25 C. The AD864 is available in 5-lead SC7 and 8-lead SOIC lead-free packages. The AD8642 is available in 8-lead MSOP and 8-lead SOIC lead-free packages. The AD8643 is available in 4-lead SOIC and 6-lead, 3 mm 3 mm, LFCSP lead-free packages. PIN CONFIGURATIONS OUT 5 AD864 VEE 2 TOP VIEW (Not to Scale) +IN 3 4 VCC IN Figure. 5-Lead SC7 (KS-5) NC IN 2 +IN 3 VEE 4 V 4 AD864 TOP VIEW (Not to Scale) 572-8 NC 7 VCC 6 OUT 5 NC 5 +IN B Figure 4. 8-Lead MSOP (RM-8) OUT A 4 OUT D IN A 2 3 IN D +IN A 3 AD8643 2 +IN D V+ 4 TOP VIEW V (Not to Scale) +IN B 5 +IN C IN B 6 9 IN C OUT B 7 8 OUT C IN A +IN A 2 V+ 3 +IN B 4 Figure 5. 4-Lead SOIC (R-4) NC OUT A OUT D NC 6 5 4 3 PIN INDICATOR AD8643 TOP VIEW IN B OUT B OUT C IN C NC = NO CONNECT 5 6 7 8 572-2 2 IN D +IN D V 9 +IN C Figure 6. 6-Lead LFCSP (CP-6) (Not Drawn to Scale) 572-5 572-64 572-3 572-4 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 78.329.47 www.analog.com Fax: 78.46.33 25 Analog Devices, Inc. All rights reserved.
AD864/AD8642/AD8643 TABLE OF CONTENTS Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 5 ESD Caution... 5 Typical Performance Characteristics... 6 Outline Dimensions... 3 Ordering Guide... 4 REVISION HISTORY 4/5 Rev. A to Rev. B Added AD8643...Universal Added 4-Lead SOIC...Universal Added 6-Lead LFCSP...Universal Updated Outline Dimensions... 3 Changes to Ordering Guide... 4 /4 Initial Version: Revision 3/5 Rev. to Rev. A Added AD8642...Universal Changes to General Description... Added Figure 3 and Figure 4... Changes to Specifications... 3 Changes to Absolute Maximum Ratings... 5 Changes to Figure 22... 8 Changes to Figure 23... 9 Changes to Figure 4... 2 Updated Outline Dimensions... 3 Changes to Ordering Guide... 4 Rev. B Page 2 of 6
SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ VS = 5. V, VCM = 2.5 V, TA = 25 C, unless otherwise noted. AD864/AD8642/AD8643 Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 5 75 µv AD8643 LFCSP only mv 4 C < TA < +85 C.5 mv +85 C < TA < +25 C, VCM =.5 V.6 mv Input Bias Current IB.25 pa 4 C < TA < +25 C 8 pa Input Offset Current IOS.5 pa 4 C < TA < +25 C 6 pa Input Voltage Range 3 V Common-Mode Rejection Ratio CMRR VCM = V to 2.5 V 74 93 db Large Signal Voltage Gain AVO RL = kω, VO =.5 to 4.5 V 8 4 V/mV Offset Voltage Drift VOS/ T 4 C < TA < +25 C 2.5 µv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH 4.95 V IL = ma, 4 C to +25 C 4.94 V Output Voltage Low VOL.5 V IL = ma, 4 C to +25 C..5 V Output Current IOUT ±6 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 5 V to 26 V 9 7 db Supply Current/Amplifier ISY 95 25 µa 4 C < TA < +25 C 27 µa DYNAMIC PERFORMANCE Slew Rate SR 2 V/µs Gain Bandwidth Product GBP AD864, AD8642 3 MHz AD8643 2.5 MHz Phase Margin Øm 5 Degrees NOISE PERFORMANCE Voltage Noise en p-p f =. Hz to Hz 4. µv p-p Voltage Noise Density en f = khz 28.5 nv/ Hz Current Noise Density in f = khz.5 fa/ Hz Rev. B Page 3 of 6
AD864/AD8642/AD8643 @ VS= ±3 V, VCM = V, TA =25 C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 7 75 µv AD8643 LFCSP only mv 4 < TA < +25 C.5 mv Input Bias Current IB.25 pa 4 C < TA < +25 C 26 pa Input Offset Current IOS.5 pa 4 C < TA < +25 C 65 pa Input Voltage Range 3 + V Common-Mode Rejection Ratio CMRR VCM = 3 V to + V 9 7 db Large Signal Voltage Gain AVO RL = kω, VO = V to + V 25 29 V/mV Offset Voltage Drift VOS/ T 4 C < TA < +25 C 2.5 µv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH +2.95 V IL = ma, 4 C to +25 C +2.94 V Output Voltage Low VOL 2.95 V IL = ma, 4 C to +25 C 2.94 V Output Current IOUT ±2 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±3 V 9 7 db Supply Current/Amplifier ISY 2 29 µa 4 C < TA < +25 C 33 µa DYNAMIC PERFORMANCE Slew Rate SR 3 V/µs Gain Bandwidth Product GBP 3.5 MHz Phase Margin Øm 6 Degrees NOISE PERFORMANCE Voltage Noise en p-p f =. Hz to Hz 4.2 µv p-p Voltage Noise Density en f = khz 27.5 nv/ Hz Current Noise Density in f = khz.5 fa/ Hz Rev. B Page 4 of 6
AD864/AD8642/AD8643 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 27.3 V Input Voltage VS to VS+ Differential Input Voltage ±Supply Voltage Output Short-Circuit Duration Indefinite Storage Temperature Range KS-5, R-8, RM-8, R-4, CP-6 Packages 65 C to +5 C Operating Temperature Range 4 C to +25 C Junction Temperature Range KS-5, R-8, RM-8, R-4, CP-6 Packages 65 C to +5 C Lead Temperature Range (Soldering, 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Type θja 2 θjc Unit 5-Lead SC7 (KS) 33.4 223.9 C/W 8-Lead SOIC (R) 57 56 C/W 8-Lead MSOP (RM) 26 44 C/W 4-Lead SOIC (R) 2 36 C/W 6-Lead LFCSP (CP) 44 3.5 C/W Absolute maximum ratings apply at 25 C, unless otherwise noted. 2 θja is specified for the worst-case conditions, that is, θja is specified for devices soldered on circuit boards for surface-mounted packages. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B Page 5 of 6
AD864/AD8642/AD8643 TYPICAL PERFORMANCE CHARACTERISTICS 8 7 2 8 V SY = 5V V CM =.5V FREQUENCY 6 5 4 3 2 NUMBER OF AMPLIFIERS 6 4 2 8 6 4 2.6.55.5.45.4.35.3.25.2.5..5.5..5.2.25.3.35.4.45.5.55.6 V OS (mv) 572-2.5..5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 6. 6.5 7. 7.5 T C V OS (µv/ C) 8. 8.5 9. 9.5. 572-5 Figure 7. Input Offset Voltage Figure. Offset Voltage Drift NUMBER OF AMPLIFIERS 6 4 2 8 6 4 2 INPUT BIAS (pa) 4.5 4. 3.5 3..5 T A = 25 C 2.5 2..5..5..5 2. 2.5 3. 3.5 4. 4.5 5. 5.5 6. 6.5 7. 7.5 8. 8.5 9. 9.5. OFFSET VOLTAGE (µv/ C) 572-3.5 5 3 9 7 5 3 3 5 7 9 3 5 V CM (V) 572-6 Figure 8. Offset Voltage Drift Figure. Input Bias Current vs. VCM 7 6 V SY = ±2.5V.5.4.3 T A = 25 C 5.2 FREQUENCY 4 3 INPUT BIAS (pa).. 2.2.3.4.6.55.5.45.4.35.3.25.2.5..5.5..5.2.25.3.35.4.45.5.55.6 V OS (mv) 572-4.5 5. 2.5. 7.5 5. 2.5 2.5 5. 7.5. 2.5 5. V CM (V) 572-7 Figure 9. Input Offset Voltage Figure 2. Input Bias Current vs. VCM Rev. B Page 6 of 6
AD864/AD8642/AD8643 5 4 V SY = 5V INPUT BIAS CURRENT (pa) V OS (µv) 3 2 2 3 4. 25 5 75 25 5 TEMPERATURE ( C) 572-8 5.5..5 2. 2.5 V CM (V) 572- Figure 3. Input Bias Current vs. Temperature Figure 6. Input Offset Voltage vs. VCM..8.6 V SY = +5V OR ±5V M INPUT BIAS (pa).4.2.2.4.6 OPEN-LOOP GAIN (V/V) M.8 k V SY = ±2.5V. 5 4 3 2 2 3 4 5 V CM (V) 572-9 k. LOAD RESISTANCE (kω) 572-2 Figure 4. Input Bias Current vs. VCM Figure 7. Open-Loop Gain vs. Load Resistance 9 A 8 B 7 6 C D V OS (µv) 5 4 3 2 A VO (V/mV) E A., V O = ±V, R L = kω B., V O = ±V, R L = 2kΩ C. V SY = +5V, V O = +.5V/+4.5V, R L = kω D. V SY = +5V, V O = +.5V/+4.5V, R L = 2kΩ E. V SY = +5V, V O = +.5V/+4.5V, R L = 6Ω 5 3 9 7 5 3 3 5 7 9 3 5 V CM (V) 572-5 3 3 5 7 9 3 5 TEMPERATURE ( C) 572-3 Figure 5. Input Offset Voltage vs. VCM Figure 8. Open-Loop Gain vs. Temperature Rev. B Page 7 of 6
AD864/AD8642/AD8643 OFFSET VOLTAGE (µv) 6 5 4 3 2 kω 2 3 4 kω kω 5 6 5 5 5 5 OUTPUT VOLTAGE (V) Figure 9. Input Error Voltage vs. Output Voltage for Resistive Loads 572-4 SATURATION VOLTAGE (mv) V SY V OH V SY V OL... LOAD CURRENT (ma) Figure 22. Output Saturation Voltage vs. Load Current 572-7 INPUT VOLTAGE (µv) 25 2 V SY = ±5V POS RAIL 5 R L = kω 5 R L = 2kΩ R L = kω V OL R L = kω 5 5 2 R 25 L = kω R L = kω R L = kω 3 NEG RAIL 35 R L = 2kΩ 5 5 2 25 3 35... OUTPUT VOLTAGE FROM SUPPLY RAIL (mv) 572-5 SATURATION VOLTAGE (mv) V SY = 5V V SY V OH LOAD CURRENT (ma) 572-8 Figure 2. Input Error Voltage vs. Output Voltage Within 3 mv of Supply Rails Figure 23. Output Saturation Voltage vs. Load Current I SY (µa) 8 7 6 5 4 3 +25 C +25 C 2 55 C 4 8 2 6 2 24 28 V SY (V) 572-6 GAIN (db) 7 6 5 4 3 2 2 GAIN 3 35 k k M M R L = 2kΩ C L = 4pF PHASE 35 27 225 8 35 9 45 45 9 PHASE (Degrees) 572-9 Figure 2. Quiescent Current vs. Supply Voltage at Different Temperatures Figure 24. Open-Loop Gain and Phase Margin vs. Frequency Rev. B Page 8 of 6
AD864/AD8642/AD8643 7 6 5 V SY = 5V R L = 2kΩ C L = 4pF 35 27 225 4 2 GAIN (db) 4 3 2 GAIN PHASE 8 35 9 45 PHASE (Degrees) CMRR (db) 8 6 4 2 45 2 2 9 3 35 k k M M 572-2 4 6 k k k M M 572-23 Figure 25. Open-Loop Gain and Phase Margin vs. Frequency Figure 28. CMRR vs. Frequency 7 6 5 R L = 2kΩ C L = 4pF 4 2 V SY =5V GAIN (db) 4 3 2 2 G = + CMRR (db) 8 6 4 G = + 2 G = + 2 4 3 k k k M M 572-2 6 k k k M M 572-24 Figure 26. Closed-Loop Gain vs. Frequency Figure 29. CMRR vs. Frequency 7 6 5 V SY = 5V R L = 2kΩ C L = 4pF 4 2 +PSRR GAIN (db) 4 3 2 G = + G = + PSRR (db) 8 6 4 2 PSRR G = + 2 2 4 3 k k k M M 572-22 6 k k k M M 572-25 Figure 27. Closed-Loop Gain vs. Frequency Figure 3. PSRR vs. Frequency Rev. B Page 9 of 6
AD864/AD8642/AD8643 4 2 V SY =5V..8 T 8 +PSRR.6.4 V IN PSRR (db) 6 4 2 PSRR INPUT BIAS (pa).2.2.4 2 2.6 V OUT 4 6 k k k M M 572-26.8. 5 CH 4.V 3 CH2 2.V M4µs 2 A 3CH 4.V5 T.s V CM (V) 572-29 572-9 Figure 3. PSRR vs. Frequency Figure 34. No Phase Reversal G = + 5 V S = ±3V GAIN = +5 TS + (%) Z OUT (Ω). OUTPUT SWING (V) 5 TS + (.%) G = + G = + 5 TS (.%) TS (%). k k k M M M 572-27 5.2.4.6.8..2.4.6.8 2. SETTLING TIME (µs) 572-3 Figure 32. Output Impedance vs. Frequency Figure 35. Output Swing and Error vs. Settling Time V SY = 5V G = + 7 6 5 V S = ±3V R L = kω V IN = mv p-p A V = + Z OUT (Ω) G = + G = + OVERSHOOT (%) 4 3 2 OS OS+.. k k k M M M 572-28 CAPACITANCE (pf) 572-3 Figure 33. Output Impedance vs. Frequency Figure 36. Small Signal Overshoot vs. Load Capacitance Rev. B Page of 6
AD864/AD8642/AD8643 OVERSHOOT (%) 7 6 5 4 3 2 V S = ±2.5V R L = kω V IN = mv p-p A V = + OS OS+ VOLTAGE NOISE DENSITY (nv/ Hz) k CAPACITANCE (pf) 572-32 k k 572-35 Figure 37. Small Signal Overshoot vs. Load Capacitance Figure 4. Voltage Noise Density INPUT BIAS (pa)..8.6.4.2.2.4.6.8. 5 CH 4.V 3 2 M.s 2 A CH 3 4 2.V5 V CM (V) V S = ±3V G = +M CH p-p = 4.26V 572-33 572-9 VOLTAGE NOISE DENSITY (nv/ Hz) k V SY = 5V k k 572-36 Figure 38.. Hz to Hz Noise Figure 4. Voltage Noise Density..8.6 V S = ±2.5V G = +M CH p-p = 4.6V.4. LOAD = kω GAIN = + 8V p-p INPUT INPUT BIAS (pa).4.2.2.4 THD + NOISE (%).. 4V p-p INPUT 2V p-p INPUT V p-p INPUT.6.8. 5 CH 4.V 3 2 M.s 2 A CH 3 4 2.V5 V CM (V) 572-34 572-9. k k 2k 572-37 Figure 39.. Hz to Hz Noise Figure 42. Total Harmonic Distortion + Noise vs. Frequency Rev. B Page of 6
AD864/AD8642/AD8643 (db) 4 5 6 7 8 9 2 3 4 5 V IN + 2kΩ 2kΩ V IN = 4.5V p-p V IN = 9V p-p 2kΩ 6 2 k k k + 2kΩ V IN = 8V p-p 572-4 Figure 43. Channel Separation Rev. B Page 2 of 6
AD864/AD8642/AD8643 OUTLINE DIMENSIONS 2.2 2..8 3. BSC.35.25.5 5 4 2 3 2.4 2..8 3. BSC 8 5 4 4.9 BSC..9.7. MAX PIN.3.5. COPLANARITY.65 BSC..8 SEATING PLANE.4..22.8 COMPLIANT TO JEDEC STANDARDS MO-23AA.3. Figure 44. 5-Lead Thin Shrink Small Outline Transistor Package [SC7] (KS-5) Dimensions shown in millimeters.5. PIN.65 BSC.38.22 COPLANARITY.. MAX SEATING PLANE.23.8 8 COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure 46. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters.8.6.4 5. (.968) 4.8 (.89) 8.75 (.3445) 8.55 (.3366).25 (.98). (.4) 8 5 6.2 (.244) 4 8 4. (.575) 6.2 (.244) 4 5.8 (.2284) 3.8 (.496) 7 5.8 (.2283).27 (.5).5 (.96) BSC.75 (.688).25 (.99) 45.27 (.5) BSC.75 (.689).5 (.97) 45.25 (.98).35 (.532).35 (.53).25 (.98). (.39) 4. (.574) 3.8 (.497) COPLANARITY. SEATING PLANE.5 (.2).3 (.22).25 (.98).7 (.67) 8.27 (.5).4 (.57) COPLANARITY..5 (.2).3 (.22) SEATING PLANE.25 (.98).7 (.67) 8.27 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 45. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) COMPLIANT TO JEDEC STANDARDS MS-2-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 47. 4-Lead Standard Small Outline Package [SOIC_N] (R-4) Dimensions shown in millimeters and (inches) Rev. B Page 3 of 6
AD864/AD8642/AD8643 PIN INDICATOR 3. BSC SQ TOP VIEW 2.75 BSC SQ.45.5.4.6 MAX.3 PIN 3 2 EXPOSED PAD 6 INDICATOR *.65.5 SQ.35.9.85.8 SEATING PLANE 2 MAX.8 MAX.65 TYP.5 BSC.5 REF 9 (BOTTOM VIEW) 4 8 5.5 MAX.2 NOM.3.2 REF.23.8 *COMPLIANT TO JEDEC STANDARDS MO-22-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION..25 MIN Figure 48. 6-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm 3 mm Body, Very Thin Quad (CP-6-3) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD864AKSZ-R2 4 C to +25 C 5-Lead SC7 KS-5 A7 AD864AKSZ-REEL7 4 C to +25 C 5-Lead SC7 KS-5 A7 AD864AKSZ-REEL 4 C to +25 C 5-Lead SC7 KS-5 A7 AD864ARZ 4 C to +25 C 8-lead SOIC_N R-8 AD864ARZ-REEL7 4 C to +25 C 8-lead SOIC_N R-8 AD864ARZ-REEL 4 C to +25 C 8-lead SOIC_N R-8 AD8642ARMZ-R2 4 C to +25 C 8-lead MSOP RM-8 AA AD8642ARMZ-REEL 4 C to +25 C 8-lead MSOP RM-8 AA AD8642ARZ 4 C to +25 C 8-lead SOIC_N R-8 AD8642ARZ-REEL7 4 C to +25 C 8-lead SOIC_N R-8 AD8642ARZ-REEL 4 C to +25 C 8-lead SOIC_N R-8 AD8643ARZ 4 C to +25 C 4-lead SOIC_N R-4 AD8643ARZ-REEL7 4 C to +25 C 4-lead SOIC_N R-4 AD8643ARZ-REEL 4 C to +25 C 4-lead SOIC_N R-4 AD8643ACPZ-R2 4 C to +25 C 6-Lead LFCSP_VQ CP-6-3 AUA AD8643ACPZ-REEL7 4 C to +25 C 6-Lead LFCSP_VQ CP-6-3 AUA AD8643ACPZ-REEL 4 C to +25 C 6-Lead LFCSP_VQ CP-6-3 AUA Z = Pb-free part. Rev. B Page 4 of 6
AD864/AD8642/AD8643 NOTES Rev. B Page 5 of 6
AD864/AD8642/AD8643 NOTES 25 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D572 4/5(B) Rev. B Page 6 of 6