CMOS Circuits 1
Combination and Sequential 2
Static Combinational Network CMOS Circuits Pull-up network-pmos Pull-down network-nmos Networks are complementary to each other When the circuit is dormant, no current flows between supply lines. Number of the NMOS transistors (PMOS transistors) equals to the number of the inputs. Output load is capacitive Inputs VDD PMOS Network NMOS Network Output 3
NAND Gates Transistors in Parallel 1/Rch eff = (1/Rch 1 ) + (1/Rch 2 ) W -- L eff = W - - L 1 + W - - L 2 (W/L) 1 (W/L) 2 (W/L) eff Transistors in Series (W/L) 1 Rch eff = Rch 1 + Rch 2 (W/L) eff W ---- L eff = W 1 ----- W 1 + ----- L 1 L 2 1 (W/L) 2 4
CMOS NAND Gate DC Analysis Two possible scenarios: 1. Both inputs are toggling 2. One input is toggling, the other one set high Assumptions: MP2=MP1=MP MN1=MN2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Inverter VTC 5
Gate Sizing To obtain equal Rise and Fall time, Size the series / parallel transistors to have an equivalent of a single PU or PD inverter transistor in your design 6
Sizing the CMOS Gate 7
NAND Gates: Analysis Scenario #1- Both inputs are toggling L-H > (W/L)eff = 2(W/L)p H-L > (W/L)eff = 1/2(W/L)n K R NAND = 1/4 K R INV Vin V OH Inverter One input toggling Scenario #2- One input is toggling L-H > (W/L)eff = (W/L)p H-L > (W/L)eff = 1/2(W/L)n K R NAND = 1/2 K R INV V OL Vin=Vout Vx2 Vx1 Two inputs toggling Vout 8
NAND Gates: Analysis Switching Analysis Scenario #1- Both inputs are toggling t PLH NAND = 1/2t PLH INVERTER t PHL NAND = 2t PHL INVERTER MP2 VDD MP1 X A MN1 CL Scenario #2- One input is toggling t PLH NAND = t PLH INVERTER t PHL NAND = 2t PHL INVERTER B MN2 9
NAND Gate: Power Dissipation P ac = α.f. C V DD 2 VDD A B X 0 0 1 1 0 1 0 1 1 1 1 0 α = P (X=1). P (X=0) assuming A and B have equal probabilities for 1 and 0 α = (1/4). (3/4)= 3/16 C = C L + C parasitic A B MP2 MP1 X MN1 MN2 CL 10
Increasing the inputs 11
NOR Gate: Analysis DC Analysis/ AC Analysis Two possible scenarios: 1. Both inputs are toggling (one is set low) 2. One input is toggling, the other one set high Assumptions: AP2=BP1=MP AN1=BN2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Compare with a CMOS inverter: MP/MN K R, and the shift in VTC Propagation delay t PLH and t PHL 12
4 INPUT NOR Gate VDD Very slow rise time and rise delays Could be compensated by increasing of PMOS transistor size. Implications: Silicon Area Input capacitance A B C D X A B C D C L 13
Practical Considerations 1. Minimize the use of NOR gates 2. Minimize the fan-in of NOR gates 3. Limit the fan-in to 4 for NAND gates 4. Use De morgan s theorem to reduce the number of fan-in per gate Example: F = ABCDEFGH = (ABCD) + (EFGH) 14
Complex CMOS Gate 15
Reducing Output Capacitance 16
Pseudo nmos 17
Pseudo nmos NAND/NOR Gates 18
Pseudo nmos Complex Gates 19
CASCODE LOGIC Lad is cross coupled pmos transistors Logic is series and parallel complementary transistors Input and Output are in Complementary forms 20
CSACODE Inverter/Nand Gate 21
CASCODE Complex Gate 22
DCVS trees for a full adder Sum and Carry Pull- Down Networks S (A,B,C) = A BC + A B C + ABC + AB C S (A,B,C) = A B C + A BC + ABC + AB C C(A,B,C) = AB + BC + AC 23
Transmission Gate Bi-directional switch, passes digital signals Less complex and more versatile than AND gate Passes analog signals A C B Problems: Large ON resistance during transitions of input signals Large input and output capacitance (useful for data storage applications) Capacitive coupling Applications: Multiplexers, encoders, latches, registers various combinational logic circuits C A B A TG C A C C C B C INV included B 24
NMOS/PMOS as Pass Transistors NMOS Transistor Vo Passes weak 1 signal Vo = V DD -V TN Passes 0 signal undegraded V DD -V TN Vi C Vo CL V DD -V TN Vi PMOS Transistor Passes 1 signal undegraded Vo Vi C Vo Passes weak 0 signal Vo= -V TP -V TP -V TP Vi CL 25
TX Gate: Characteristics C Vo Vin Vo Vin R nmos:sat nmos:sat nmos:off pmos:sat pmos:lin pmos:lin Req,p Req,n 0V V TP V DD -V TN V DD Req,TX 0 VDD-VTN VDD Vo 26
AND, NAND A B F 0 0 0 0 1 0 1 0 0 1 1 1 27
OR, NOR A B F 0 0 0 0 1 1 1 0 1 1 1 1 28
A multiplexer C A B F C A B F 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 29
XOR A B F 0 0 0 0 1 1 1 0 1 1 1 0 30
Four to one multiplexer 31
TX Gate: Layout C VDD P+ P+ Vi VO N+ N+ C VSS C C For data path structure 32
NAND Gates: Layout Layout Transistors in Series Transistors in Parallel 33
NAND Gates: Layout VDD Metal II A B X Via GND 34
NOR Gate: Layout V DD X B A GND 35
Analysis and Design of Complex Gate Analysis p+ layer A B C D E F 1. Construct the schematic 2. Determine the logic function. 3. Determine transistor sizes. 4. Determine the input pattern to cause slowest and fastest operations. 5. Determine the worst case rise delay (t PLH )and fall delay (t PHL ) 6. Determine the best case rise and fall delays. contact N-well VDD GND OUT A B C D n+ layer polysilicon metal E F active (diffusion) 36