Low Transistor Variability The Key to Energy Efficient ICs

Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Overview Where does the power go? From your smartphone to the cloud Why is transistor variability important? Billions of very small transistors Little things matter a lot What can be done now? Reduce transistor variability Improve existing mainstream CMOS IC technology 2 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Semiconductor Industry Energy efficiency and power are now the dominant issues Mobile electronics everywhere We are all affected by the limited battery life Computing in the cloud Where Internet searches take place and voice recognition processes your speech Power ~ CV 2 f + IV Switching/active power Leakage/static power To lower power, Voltage (V = V DD ) needs to be decreased 3 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Let s Look at a Real Chip: AMD Bulldozer Memory/SRAM 50% chip area Leakage power dominant Digital logic 40% chip area At full speed active (switching) power dominant At reduced speed static (leakage) power dominant Analog I/O 10% chip area (periphery) Always drawing current in the on state Billions of transistors Transistor variability impacts dynamic, leakage, and analog power Source: www.anandtech.com/ 4 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

[#Transistors] [Leakage Power] Impact of Transistor Variability: Leakage High leakage tail dominates power 2.7x higher power (85mV subv T slope) High leakage tail High V T tail Slows down ICs Transistor variability is reflected in threshold voltage (V T ) distribution Leakage current is exponentially dependent on V T Lower V T variability (sv T ) reduces number of leaky low V T devices Power dissipation is dominated by low V T edge of distribution Smaller sv T Less leakage power for digital and memory/sram 5 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

[NCP] Impact of Transistor Variability on Digital Logic (A) (C) (D) (B) Delay [ps] ICs have thousands of timing critical paths (A) Varying for each part due to transistor variability Slowest path determines chip frequency (B) Lower variability results in tighter distribution and faster chips (C) Reduce V DD to match worst case speed (D) Large effect on active power as it is proportional to V 2 6 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Lowering V DD in ICs Traditional CMOS IC technologies are stuck around 1V V DD for the last 10 years Typical voltage scaling limited to 0.9V (10%) Minimal benefit for overhead and risk Lowering V DD is limited by SRAM/Memory Built using 6-T(ransistor) SRAM cells using billions of the smallest transistors Transistor matching critical for functionality Transistor mismatch causes SRAM failures Cell cannot be written (write margin) Cell cannot be read (read margin) Cell is too slow (read current) Reducing transistor variation will lower minimum V DD 7 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Impact of Transistor Variability in Analog Analog & Mixed Signal circuits 10% of area in digital SOC (mostly I/O) Up to 50% or more area in analog chips Focus on matching transistors Differential pair, current mirrors, etc. Reducing relative variability by making transistors bigger Larger transistors have higher parasitic capacitances limiting performance Larger transistors require higher power Lower variability transistors enables Area savings Higher performance Lower power SuVolta sample layout 8 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Energy Efficiency in an SOC IC Putting it all together Achieve same performance with lower V DD Take full advantage of voltage scaling lowering V DD Lower active power due to lower V DD Lower leakage power due to reduced transistor variability Much lower energy consumption in real life application Smartphone Application Processor Usage Legacy Low Variability Type [mins] [GHz] Vdd Power Vdd Power Game 10 1.000 1.00 1.000 0.95 0.810 WebApp 20 0.500 0.90 0.554 0.75 0.338 Email 60 0.100 0.90 0.327 0.60 0.121 Minimal 1350 0.001 0.85 0.256 0.50 0.080 Battery Life [days] 1 3.0 9 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Where Does Transistor Variability Come From? Source: Asenov, University of Glasgow, GSS Statistical variability dominates over systematic variability Random dopant fluctuations (RDF) Polysilicon or high-k granularity Line edge roughness (LER) RDF dominant contributor to transistor variability 10 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

DDC Transistor Benefits Depleted channel remove dopants out of channel Low random dopant fluctuation (RDF) Reduced transistor variability Inserted in traditional planar bulk CMOS Leveraging existing tool, manufacturing, design flow Leveraging existing design libraries Multi-V T capable Transistor architecture details will be disclosed at IEDM in Washington DC in early December. 12 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

65nm Silicon Results Nominal V DD reduced from 1.2V to 0.9V Reduces active power by around 50% Speed remains constant Transistor variation reduced by 50% 65nm 2RW SRAM NMOS pull-down transistors Silicon proven at advanced nodes 13 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Block counts 5x Leakage Power Reduction on SRAM SRAM leakage power decreases 5x from 840 μw to 170 μw 222M transistors measured ~ 170 μw leakage power DDC 0.9V No design change High yield ~840 μw leakage power Conventional 1.2V 65nm 2RW SRAM Array Silicon Data 14 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Lower Transistor Variability Improves SRAM Improved read stability (static noise margin SNM) Lower SRAM minimum operating voltage V Min Lower minimum V DD retention voltage (better standby power) Better write margin Much lower array leakage Worst-case devices (tail) dominate Faster SRAM operation Lower read current variability 92mV 28nm Baseline 28nm Baseline BL = 52mV 28nm Baseline 9.9uA 28nm DDC 28nm DDC BL = 190mV 28nm DDC 147mV 18.2uA 15 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Impact of Variability on SRAM Speed Statistical Monte-Carlo simulation analysis of SRAM read delay 50% lower variability improves speed by 40% V DD can be reduced to match worst case speed 28nm Baseline 28nm DDC 530ps 374ps 16 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Industry Norm Sub 0.5V V Min is Possible SRAM blocks limit V DD scaling V min lowest operating voltage limited by transistor mismatch Below 0.5V V Min SRAMs Demonstrated at 65nm Conventional SRAMs are 0.8V+ DDC 300 mv Standard SRAM macros No circuit tricks for low voltage operation Demonstrates potential for 50% voltage scaling Tester limit 17 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

420um 210um Design Examples Analog OpAmp stage Matched bandwidth, gain, slewrate Over 50% smaller area (84 vs 190μm 2 ) 45% better input noise (176 vs 327 μv) Bandgap reference circuit Same accuracy achieved at half the size Baseline 10.9x17.4um DDC 6.9x12.2um Much improved energy efficiency Smaller load Reduced area reduces chip power Baseline 450um SuVolta sample layout DDC 450um 18 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

DDC Transistor Technology Undoped channel in bulk planar CMOS Supports thin oxide, thick oxide, digital, analog, HV devices Improved body coefficient enables effective body biasing Tighten systematic variation Further reduce leakage power Compensate V T variation due to temperature fluctuations at low V DD Parameters V T variation (sv T ) Channel mobility Benefits proven with silicon 2x reduction 10% I EFF increase at 0.85V (matched C-overlap) Device impact reduced leakage and reduced V min increased I EFF DIBL 20% reduction scaling enabled Body coefficient 2x increase increased V T control Chip impact reduced power increased performance increased density reduced power 19 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.

Summary Energy efficiency and power dominate IC design Voltage is the strongest lever to achieve lower power Transistor variability limits today s CMOS technologies Affecting IC voltage scaling Affecting IC size and performance Deeply Depleted Channel (DDC) technology drastically reduces transistor variability Half the power at the same performance SRAM operation at less than 0.5V 5x lower leakage Compatible with existing planar bulk CMOS technologies Compatible with existing design flows and circuit IP 20 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc. All rights reserved.