VLSI esign Last module: Wire resistance and capacitance RC delay Wire gineering This module Floorplanning (basic physical design determines wires) Sequtial circuit design Clock skew Floorplan How do you estimate block areas? Begin with block diagram Each block has Inputs Outputs Function (draw schematic) Type: array, datapath, random logic Estimation depds on type of logic. Z. Pan 1. Z. Pan 2 5000 λ 1690 λ 3500 λ MIPS Floorplan mips (4.6 Mλ2) control 1500 λ x 400 λ (0.6 Mλ2) alucontrol 200 λ x 100 λ wiring channel: 30 tracks = 240 λ (20 kλ2) zipper 2700 λ x 250 λ datapath 2700 λ x 1050 λ (2.8 Mλ2) bitslice 2700 λ x 100 λ 2700 λ 3500 λ 5000 λ. Z. Pan 3 Area Estimation Arrays: Layout basic cell Calculate core area from # of cells Allow area for decoders, column circuitry atapaths Sketch slice plan Count area of cells from cell library Ensure wiring is possible Random logic Compare complexity do a design you have done. Z. Pan 4 writedata memdata adr adrmux IR3...0 writemux MR MIPS Slice Plan srcb bitlines srca aluresult immediate pc aluout 44 24 93 93 93 93 93 44 24 52 48 48 48 48 16 86 93 93 44 24 93 93 24 44 39 39 39 39 160131 131 131 writedriver dualsram dualsram dualsram dualsrambit0 srampullup readmux mux4 register file srcb srca ramslice aluout. Z. Pan 5 mux4 and2 PC and2 zerodetect and2 ALU or2 fulladder mux4 Typical Layout sities Typical numbers of high-quality layout erate by 2 for class projects to allow routing and some sloppy layout. Allocate space for big wiring channels Elemt Area Random logic (2 metal layers) 1000-1500 λ 2 / transistor atapath 250 750 λ 2 / transistor Or 6 WL + 360 λ 2 / transistor SRAM 1000 λ 2 / bit RAM 100 λ 2 / bit ROM 100 λ 2 / bit. Z. Pan 6. Z. Pan 1
VLSI esign Sequcing logic output depds on currt inputs Sequtial logic output depds on currt and previous inputs Requires separating previous, currt, future Called state or toks Ex: FSM, pipeline in Finite State Machine out Pipeline. Z. Pan 7 Sequcing Cont. If toks moved through pipeline at constant speed, no sequcing elemts would be necessary Ex: fiber-optic cable Light pulses (toks) are st down cable Next pulse st before first reaches d of cable No need for hardware to separate pulses But dispersion sets min time betwe pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast toks so they don t catch slow ones.. Z. Pan 8 Sequcing Overhead Use flip-s to delay fast toks so they move through exactly one stage each cycle Inevitably adds some delay to the slow toks Makes circuit slower than just the logic delay Called Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequce. Z. Pan 9 Sequcing Elemts : Level ssitive a.k.a. transpart latch, latch Flip-: edge triggered A.k.a. master-slave flip-, flip-, register Timing iagrams Transpart Opaque Edge-trigger (latch) (). Z. Pan 10 Sequcing Elemts : Level ssitive a.k.a. transpart latch, latch Flip-: edge triggered A.k.a. master-slave flip-, flip-, register Timing iagrams Transpart Opaque Edge-trigger (latch) (). Z. Pan 11 esign Pass Transistor Pros +Tiny + Low clock load Cons V t drop nonrestoring backdriving output noise ssitivity dynamic diffusion input. Z. Pan 12 Used in 1970s. Z. Pan 2
VLSI esign esign esign Transmission gate +No V t drop - Requires erted clock Inverting buffer +Restoring + No backdriving + Fixes either Output noise ssitivity Or diffusion input Inverted output Tristate feedback + Static Backdriving risk Static latches are now esstial Buffered input + Fixes diffusion input + Nonerting. Z. Pan 13. Z. Pan 14 esign esign Buffered output + No backdriving atapath latch + Smaller, faster - unbuffered input Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading. Z. Pan 15. Z. Pan 16 Flip- esign Flip- is built as pair of back-to-back latches Enable Enable: ignore clock wh = 0 Mux: increase latch - delay Clock Gating: increase setup time, skew Symbol Multiplexer esign Clock Gating esign 1 0 1 0. Z. Pan 17. Z. Pan 18. Z. Pan 3
VLSI esign Reset Force output low wh asserted Synchronous vs. asynchronous Symbol Set / Reset Set forces output high wh abled Flip- with asynchronous set and Synchronous Reset Asynchronous Reset set set. Z. Pan 19. Z. Pan 20 Sequcing Methods Timing iagrams Flip-s 2-Phase es Pulsed es Flip-s 2-Phase Transpart es Pulsed es 1 2 p 1 2 1 t pw p /2 Half-Cycle 1 Half-Cycle 1 p q q Contamination and Propagation elays Prop. elay Cont. elay / Clk- Prop elay / Clk- Cont. elay - Prop elay - Cont. elay / Setup Time / Hold Time A Y A Y thold q q. Z. Pan 21. Z. Pan 22 Illustration of delays Master-Slave Flip- Max-elay: Flip-s -( + ) I 2 I 1 T 2 T 1 I 3 I 5 T 4 M I 4 T 3 I 6 1 2 K = = 1 = igital Integrated Circuits 2nd 2. Z. Pan 23. Z. Pan 24. Z. Pan 4
VLSI esign Max elay: 2-Phase es = 1 + 2 -(2q ) Max elay: Pulsed es -max(q, + -t pw ) 1 2 1 p p 1 1 2 2 3 1 2 L3 3 1 1 2 2 1 1 q 2 (a) t pw > 1 1 q1 2 1 1 p 2 q2 1 t pw tpd tsetup 2 2 (b) t pw < 2 3. Z. Pan 25. Z. Pan 26 t t t cd hold ccq Min-elay: Flip-s 1 Min-elay: 2-Phase es t t t t t cd1, cd 2 hold ccq nonoverlap 1 1 2 Hold time reduced by nonoverlap 2 2 1 2 Paradox: hold applies twice each cycle, vs. only once for s. But a is made of two latches! 1 2 1 2. Z. Pan 27. Z. Pan 28 t t t + t Min-elay: Pulsed es cd hold ccq pw Hold time increased by pulse width 2 p 1 2 p p tpw 1. Z. Pan 29 Time Borrowing In a -based system: ata launches on one rising edge Mus before next rising edge If it arrives late, system fails If it arrives early, time is wasted s have hard edges In a latch-based system ata can pass through latch while transpart Long cycle of logic can borrow time into next As long as each loop completes in one cycle. Z. Pan 30. Z. Pan 5
VLSI esign Time Borrowing Example How Much Borrowing? 1 2 1 1 2 2-Phase es t T c ( tsetup + t ) borrow nonoverlap 2 1 2 1 1 2 2 1 (a) Pulsed es 1 2 Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary t t t borrow pw setup /2 Nominal Half-Cycle 1 elay 2 t borrow 1 2 (b) Loops may borrow time internally but must complete within the cycle. Z. Pan 31. Z. Pan 32 Clock Skew Skew: Flip-s We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing -( + + t skew ) - + t skew 1 1 2 1 q 2 t skew 2 t skew 1 2. Z. Pan 33. Z. Pan 34 2-Phase es -(2q ) 1,2 - - + t skew t borrow /2 - ( + + t skew ) Pulsed es -max(q, + -t pw +t skew ) + t pw - + t skew t borrow t pw -( + t skew ) Skew: es 1 2 1 2 1 1 1 2 2 3 1 2. Z. Pan 35 L3 3 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2). Z. Pan 36. Z. Pan 6
VLSI esign Safe Flip- In class, use flip- with nonoverlapping clocks Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk Summary Flip-s: Very easy to use, supported by all tools 2-Phase Transpart es: Lots of skew tolerance and time borrowing Pulsed es: Fast, some skew tol. & borrow, hold time risk 2 1 2 1 2 1 2 1. Z. Pan 37. Z. Pan 38. Z. Pan 7