l Logic-Level Gate Drive l dvanced Process Technology l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully valanche Rated l Lead-Free Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. G IRL2505PbF HEXFET Power MOSFET D S PD -95622 V DSS = 55V R DS(on) = 0.008Ω I D = 04 The TO-220 is universally preferred for all commercial- Industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. bsolute Maximum Ratings TO-220B Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ 0V 04 I D @ T C = C Continuous Drain Current, V GS @ 0V 74 I DM Pulsed Drain Current 360 P D @T C = 25 C Power Dissipation 200 W Linear Derating Factor.3 W/ C V GS Gate-to-Source Voltage ± 6 V E S Single Pulse valanche Energy 500 mj I R valanche Current 54 E R Repetitive valanche Energy 20 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds 300 (.6mm from case ) Thermal Resistance Mounting torque, 6-32 or M3 srew 0 lbf in (.N m) Parameter Typ. Max. Units R θjc Junction-to-Case 0.75 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θj Juction-to-mbient 62 www.irf.com 8/3/04
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.035 V/ C Reference to 25 C, I D = m 0.008 V GS = 0V, I D = 54 R DS(on) Static Drain-to-Source On-Resistance 0.00 Ω V GS = 5.0V, I D = 54 0.03 V GS = 4.0V, I D = 45 V GS(th) Gate Threshold Voltage.0 2.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 59 S V DS = 25V, I D = 54 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage V GS = 6V n Gate-to-Source Reverse Leakage - V GS = -6V Q g Total Gate Charge 30 I D = 54 Q gs Gate-to-Source Charge 25 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 67 V GS = 5.0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 2 V DD = 28V t r Rise Time 60 I D = 54 ns t d(off) Turn-Off Delay Time 43 R G =.3Ω, V GS = 5.0V t f Fall Time 84 R D = 0.50Ω, See Fig. 0 L S Internal Source Inductance 7.5 nh Between lead, and center of die contact C iss Input Capacitance 5000 V GS = 0V C oss Output Capacitance pf V DS = 25V C rss Reverse Transfer Capacitance 390 ƒ =.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 04 (Body Diode) showing the G I SM Pulsed Source Current integral reverse 360 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 54, V GS = 0V t rr Reverse Recovery Time 40 20 ns T J = 25 C, I F = 54 Q rr Reverse Recovery Charge 650 970 nc di/dt = /µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) V DD = 25V, starting T J = 25 C, L = 240µH R G = 25Ω, I S = 54. (See Figure 2) ƒ I SD 54, di/dt 230/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature;for recommended current-handling of the package refer to Design Tip # 93-4 2 www.irf.com
I D, Drain-to-Source Current () 0 VGS TOP 5V 2V 0V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH T J = 25 C 0. 0 V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current () 0 VGS TOP 5V 2V 0V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH T J = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current () 0 T = 25 C J T = 75 C J V DS= 25V 20µs PULSE WIDTH 2.5 3.5 4.5 5.5 6.5 7.5 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 2.5 I D = 90 2.0.5.0 0.5 V GS = 5V 0.0-60 -40-20 0 20 40 60 80 20 40 60 80 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 0 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 8000 C oss = C ds Cgd C iss 6000 4000 C oss 2000 C rss 0 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 5 2 9 6 3 0 I D = 54 V DS = 44V V DS = 28V FOR TEST CIRCUIT SEE FIGURE 3 0 40 80 20 60 200 Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () T = 75 C J T = 25 C J V GS = 0V 0 0.4 0.8.2.6 2.0 2.4 2.8 V SD, Source-to-Drain Voltage (V) I D, Drain Current () OPERTION IN THIS RE LIMITED BY RDS(on) 0µs µs ms 0 0ms T C = 25 C T J = 75 C Single Pulse 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea 4 www.irf.com
20 LIMITED BY PCKGE R G V GS D.U.T. - V DD I D, Drain Current () 80 60 40 20 Fig 0a. Switching Time Test Circuit V DS 90% 5.0V Pulse Width µs Duty Factor 0. % 0 25 50 75 25 50 75 T C, Case Temperature ( C) 0% V GS t d(on) t r t d(off) t f Fig 9. Maximum Drain Current Vs. Case Temperature Fig 0b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0.0 0.05 t 0.02 SINGLE PULSE t2 0.0 (THERML RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
L V DS D.U.T. R G V - DD 5.0 V I S t p 0.0Ω Fig 2a. Unclamped Inductive Test Circuit V (BR)DSS t p V DD E S, Single Pulse valanche Energy (mj) 200 800 600 400 200 TOP BOTTOM ID 22 38 54 V DD = 25V 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) V DS I S Fig 2b. Unclamped Inductive Waveforms Fig 2c. Maximum valanche Energy Vs. Drain Current Current Regulator Same Type as D.U.T. 50KΩ 5.0 V Q GS Q G Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3m Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit IRL2505PbF D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =0V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For N-Channel HEXFETS www.irf.com 7
TO-220B Package Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.03) 0.54 (.45) 0.29 (.405) 3.78 (.49) 3.54 (.39) - - 4.69 (.85) 4.20 (.65) - B -.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) 4.09 (.555) 3.47 (.530) 2 3 4 6.47 (.255) 6.0 (.240).5 (.045) MIN 4.06 (.60) 3.55 (.40) LED SSIGNMENTS LED SSIGNMENTS HEXFET IGBTs, CoPCK - GTE - GTE 2 - DRIN - GTE 2- DRIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRIN 3- EMITTER 4- DRIN 4- COLLECTOR 3X.40 (.055).5 (.045) 2.54 (.) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.04) DIMENSIONING & TOLERNCING PER NSI Y4.5M, 982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220B. 2 CONTROLLING DIMENSION : INCH 4 HETSINK & LED MESUREMENTS DO NOT INCLUDE BURRS. TO-220B Part Marking Information EXMPLE: T HIS IS N IRF00 LOT CODE 789 S S EMBLED ON WW 9, 997 IN THE SSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ERNT IONL RE CT IFIER LOGO S S E MB L Y LOT CODE PRT NUMBER DTE CODE YER 7 = 997 WEEK 9 LINE C Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market Qualification Standards can be found on IR s Web site. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (30) 252-705 TC Fax: (30) 252-7903 Visit us at www.irf.com for sales contact information.08/04 8 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/