N-Channel Enhancement Mode Low Q g and R g High dv/dt Nanosecond Switching Ideal for Class C, D, & E Applications Symbol Test Conditions Maximum Ratings V DSS T J = 2 C to 1 C V V DGR T J = 2 C to 1 C; R GS = 1 MΩ V V GS Continuous ±2 V V GSM Transient ±3 V I D2 T c = 2 C 9. A I DM T c = 2 C, pulse width limited by T JM 4 A I AR T c = 2 C 14 A E AR T c = 2 C 7. mj dv/dt I S I DM, di/dt A/µs, V DD V DSS, T j 1 C, R G =.2Ω. V/ns I S = >2 V/ns P DC 2 W P DHS T c = 2 C Derate 4.4W/ C above 2 C 8 W P DAMB T c = 2 C 3. W R thjc.74 C/W R thjhs 1. C/W Symbol Test Conditions Characteristic Values T J = 2 C unless otherwise specified min. typ. max. V DSS V GS = V, I D = 3 ma V V GS(th) V DS = V GS, I D = 4 ma 2 2.8 V I GSS V GS = ±2 V DC, V DS = ± na I DSS V DS =.8 V DSS T J = 2 C V GS = T J = 12 C R DS(on) V GS = 1 V, I D =.I D2 Pulse test, t 3µS, duty cycle d 2% 2 2 µa µa.16 Ω g fs V DS = 1 V, I D =.I D2, pulse test 2. 3. S T J - +17 C T JM 17 C T stg - +17 C T L 1.6mm(.63 in) from case for s 3 C Weight 2 g DE1-1N9A GATE SG1 Features V DSS = V I D2 = 9. A R DS(on).16 Ω P DC = 2 W SG2 Isolated Substrate high isolation voltage (>2V) excellent thermal transfer Increased temperature and power cycling capability IXYS advanced low Q g process Low gate charge and capacitances easier to drive faster switching Low R DS(on) Very low insertion inductance (<2nH) No beryllium oxide (BeO) or other hazardous materials Advantages SD1 SD2 DRAIN Optimized for RF and high speed switching at frequencies to >MHz Easy to mount no insulators needed High power density
Symbol Test Conditions Characteristic Values (T J = 2 C unless otherwise specified) DE1-1N9A min. typ. max. R G Ω C iss 7 pf C oss V GS = V, V DS =.8 V DSS(max), f = 1 MHz 2 pf C rss 3 pf C stray Back Metal to any Pin 16 pf T d(on) 4 ns T on V GS = 1 V, V DS =.8 V DSS 4 ns I D =. I DM T d(off) R G =.2 Ω (External) 4 ns T off 4 ns Q g(on) 22 nc Q gs V GS = V, V DS =. V DSS I D =. I D2, Ig = 3 ma 3.4 nc Q gd 9.1 nc -Drain Diode (T J = 2 C unless otherwise specified) Characteristic Values Symbol Test Conditions min. typ. max. I S V GS = V 9. A I SM Repetitive; pulse width limited by T JM 4 A V SD I F = I S, V GS = V, Pulse test, t 3 µs, duty cycle 2% 1. V T rr 3 ns CAUTION: Operation at or above the Maximum Ratings values may impact device reliability or cause permanent damage to the device. Information in this document is believed to be accurate and reliable. IXYSRF reserves the right to make changes to information published in this document at any time and without notice. For detailed device mounting and installation instructions, see the Device Installation & Mounting Instructions technical note on the IXYSRF web site at; http://www.ixysrf.com/pdf/switch_mode/appnotes/7de_series_mosfet_installation_instructions.pdf IXYS RF reserves the right to change limits, test conditions and dimensions. IXYS RF MOSFETS are covered by one or more of the following U.S. patents: 4,83,92 4,86,72 4,881,6 4,891,686 4,931,844,17,8,34,796,49,961,63,37,187,117,237,481,486,71,381,2,64,4
Fig. 1 Typical Transfer Characteristics Fig. 2 V DS = 3V PW = 2µS ID, Drain Current (A) 4 4 3 3 2 2 1 3. 4.. 6. 7. 8. 9. V GS, Gate-to Voltage (V) Fig. 3 Fig. 4 Gate Charge vs. Gate-to- Voltage V DS = V I D = 4.A Gate-to- Voltage (V) 14 12 8 6 4 2 1 2 2 3 3 Gate Charge (nc) ID, Drain Currnet (A) ID, Drain Currnet (A) 2 1 4 4 3 3 2 2 1 7V to V DE1-1N9A Typical Output Characteristics 4V 1 2 2 3 3 4 4 Top Bottom V DS, Drain-to- Voltage (V) Extended Typical Output Characteristics V 9V 8V 7V 6.V 6V.V V 4.V 4V 2 3 4 V DS, Drain-to- Voltage (V) 6.V 6V.V V 4.V Fig. V DS vs.capacitance Capacitance (pf) Ciss Coss Crss 1 2 3 4 6 7 8 V DS Voltage (V)
DE1-1N9A Fig. 6 Package Drawing Gate Drain
1N9A DE-SERIES SPICE Model The DE-SERIES SPICE Model is illustrated in Figure 7. The model is an expansion of the SPICE level 3 MOSFET model. It includes the stray inductive terms L G, L S and L D. Rd is the R DS(ON) of the device, Rds is the resistive leakage term. The output capacitance, C OSS, and reverse transfer capacitance, C RSS are modeled with reversed biased diodes. This provides a varactor type response necessary for a high power device model. The turn on delay and the turn off delay are adjusted via Ron and Roff. DE1-1N9A Figure 7 DE-SERIES SPICE Model This SPICE model may be downloaded as a text file from the IXYSRF web site at http://www.ixysrf.com/products/switch_mode.html http://www.ixysrf.com/spice/de1-1n9a.html Net List: *SYM=POWMOSN.SUBCKT 1N9A 2 3 * TERMINALS: D G S * Volt 9 Amp.16 ohm N-Channel Power MOSFET -3-21 M1 1 2 3 3 DMOS L=1U W=1U RON 6 1. DON 6 2 D1 ROF 7.2 DOF 2 7 D1 D1CRS 2 8 D2 D2CRS 1 8 D2 CGS 2 3.7N RD 4 1.16 DCOS 3 1 D3 RDS 1 3.MEG LS 3 3.1N LD 4 1N LG 2 1N.MODEL DMOS NMOS (LEVEL=3 VTO=3. KP=9.).MODEL D1 D (IS=.F CJO=1P BV= M=. VJ=.6 TT=1N).MODEL D2 D (IS=.F CJO=1P BV= M=. VJ=.6 TT=1N RS=M).MODEL D3 D (IS=.F CJO=3P BV= M=.3 VJ=.4 TT=4N RS=M).ENDS Doc #92-242 Rev 29 IXYS RF An IXYS Company 241 Research Blvd., Suite 8 Fort Collins, CO USA 826 97-493-191 Fax: 97-493-193 Email: sales@ixyscolorado.com Web: http://www.ixyscolorado.com