Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3

Drain Gate G V + DD D V + DD I DS D A F S V SS A V SS n MOS Inverter n-channel Depletion mode as active resistor and enhancement mode output stage MOSFET Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4 S

Drain Gate G V + DD D V + DD I DS B F A + B A.B S V SS A V SS n MOS NOR n channel Depletion mode as active resistor and two enhancement mode MOSFETs in parallel Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5 S

Drain Gate G V + DD D V + DD I DS B F A. B A +B S V SS A V SS n MOS NAND n channel Depletion mode as active resistor and two enhancement mode MOSFETs in series Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6 S

n-channel depletion mode active resistor A depletion mode n-channel MOSFET T acts as an active pull up load (in place of R, which occupies larger silicon area). Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7

n-channel enhancement mode ON state (Input Logic State 1 Output 0) When V GS >V T GS, a channel is formed between drain and source I D increases and linearly varies with V DS MOSFET ON state. Further, when the V GS increases, the slope of change in I D is steeper and steeper with respect to V DS. Channel resistance decreases steeply with (V GS - V T GS ). MOSFET is said to be in ON state. Channel width is constant is function of (V GS -V T ). GS Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8

Two enhancement mode MOSFETS in parallel Two enhancement-mode n-channel MOSFETs TA and TB are the logic drivers in parallel. These give an output Vo at F through a common point connected to drains of TA and TB. If both TA and TB are off, the output equals, supply voltage VDD. If any one is ON, the output at F equals the VSS (the supply GND) Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9

Two enhancement mode MOSFETS in Series Two enhancement mode n-channel MOSFETs T and T are in series. A B These give an output V at F through o the upper NMOS drain of T, which B also connects the NMOS MOSFET pull up. If both TA and T are off, the B output equals, supply voltage V. If DD any one is ON, the output at F equals the V (the supply GND). SS Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10

Output at F Property of a NAND is that its output is 0 when all the inputs are 1. When two enhancement mode MOSFETs are placed in series, the circuit functions as NAND Property of a NOR is that its output is 1 when all the inputs are 0. When two enhancement mode MOSFETs are placed in parallel, the circuit functions as NOR Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11

n MOS Outline n MOS Features Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12

n MOS Voltage Levels (8086) Supply V DD = 5.0 +- 0. 5VV V SS = 0V V OL (Voltage Output at logic 0 ) = 0.45V and I OL = 2mA V OH (Voltage Output at logic 1 ) = 2.4 V and I OH = -400 µa V IL (Voltage Input at logic 0 ) = 0.8V V V IH (Voltage Input at logic 1 ) = 2 V Input Leakage current = +10 µa Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13

n MOS Voltage Levels Output Leakage current = +10 µa Noise Margin at 1 = 0.4V Noise Margin at 0 = 0.4V Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14

Power Dissipation 0.2 to 10 mw Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15

Fan out and Maximum Operation Frequency Fan out 20 Maximum Operation frequency 2 MHz typical (8085) Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16

Propagation Delay 300 ns in a typical VLSI Let gate-source capacitance = C nf [nf means nanofarad.] If m = 40, the total capacitance being all T j in parallel = 40C. Resistance is very high between gate and source in both logic 0 and logic 1 states. Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17

Propagation Delay Therefore, MOSFET turn-on delay is large. Now the technology has been developed to get very small C to get the speeds compatible with TTLs Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18

Summary Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19

We learnt n MOS inverter circuit n MOS NOR circuit n MOS NAND circuit Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20

A depletion mode n MOSFET functions as active pull up resistor from supply Inverter uses one n-mosfet as an input Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21

n MOS gate has each input connection to a gate of n channel enhancement mode MOSFET Two input NOR has two n-mosfets in parallel Two input NAND has two n- MOSFETs in series Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 22

Summary Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 23

End of Lesson 8 n MOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 24

THANK YOU Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 25