Time-Delay Analysis on Grid-Conneced Three- Phase Curren Source Inverer based on SVPWM swiching paern Arman Sargolzaei 1, Amirhasan Moghadasi 2 Deparmen of Elecrical and Compuer Engineering Florida Inernaional Universiy Miami, FL 1 asarg1@fiu.edu, 2 amogh4@fiu.edu Kang Yen 3, Arif I. Sarwa 4 Deparmen of Elecrical and Compuer Engineering Florida Inernaional Universiy Miami, FL 3 yenk@fiu.edu, 4 asarwa@fiu.edu Absrac Time delays exis in mos of he elecronic componens, digial conrollers and DSPs. Cerain values of ime delay can easily corrup he performance of a power conrol sysem. This ime delay can sricly disurb he sysem dynamic in power conrol applicaions wih low o medium swiching frequency. In his paper, we overcome he effec of ime delay in an SVPWM based swiching paern for a grid conneced hreephase curren source inverer. The ime delay is racked in real ime and he saes of he sysem are esimaed. Our experimenal resuls clearly show ha he proposed approach can compensae he effec of he ime delay and improve he qualiy of he performance. Keywords Curren source inverer (CSI); ime dealy observer predicor I. INTRODUCTION Susainable energy (SE) is he fuure energy sources. However, in order o use SE sources efficienly, i s necessary o inegrae hem o a power-grid. For his purpose, inverers and elecronic circuis are needed [1, 2]. These inerface elecronic circuis are recognized as he SE inverers. The SE inverers should conver direc curren (DC) o alernaing curren (AC) wih as lile harmonic conen as possible. To do so, hey should be designed o harmonize heir oupus wih he uiliy grid line. There are many differen opologies for SE inverers, such as curren source boos inverers (CSBIs) [3-5], volage source inverers (VSIs) [5], muli-level inverers [7, 8], and marix converers [9, 1]. VSIs have many advanages and have been used in many indusrial applicaions [11]. However, despie oher ype of inverers CSBIs can inver and boos curren in a single sage from a DC source, such as phoovolaic cells, o an AC volage [12]. This advanage recognizes CSBIs inverers o one of he bes choices for SE grid conneced conversion sysems. Here we will consider he swiching paern and circui opology of he hree-phase CSBI proposed in [13]. The suggesed CSBI offers a robus mehod in he conrol of he volage and he injeced power based on is novel swiching paern. However, he proposed CSBI does no consider he ime delay effecs of hardware, sofware and componens on grid synchronizaion. Furhermore, resuls show more harmonics and less curren waveform qualiy and in some cases, he proposal is no very reliable. Mos of inverers can be conrolled wih digial signal processors (DSPs). DSPs offer high performance in feedback conrol as well as user flexibiliy for design and implemenaion. However ime delay exiss in elecronic componens and microprocessors. Here in conrolling CSBIs, we will face he ime delay in he componens and DSP. In a DSP sysem, here is a predicable effecing ime delay in each sampling cycle [14]. This delay has significan effec on swiching conrol, monioring and feedback conrol of he CSBI [13]. In advanced DSPs, he delay beween he sampling ime and he generaing SVPWM swiching ime could be longer han a sampling cycle [14]. As in power applicaions, he swiching frequency is medium and requires fas dynamic, hus i s possible o dissaisfy rule of humb for converer swiching frequency. These resuls degrade he performance of he sysem as well as he resynchronizaion hereby creaing bad qualiy in sinusoidal waveform. In his effor, we focus on ime-delay effec on grid conneced CSBI swiching paern. This paper organizes as follows: In Secions II and III, we discuss he SVPWM based swiching paern for a grid conneced hree-phase curren source inverer and he circui opology proposed by [13]. Then, we show he effec of ime delay on dspace and discuss our proposed echnique o overcome his issue. In Secion IV, we will show our pracical resuls using our proposed echnique which produces less harmonic and higher waveform qualiy. Finally we provide conclusion and possible fuure works. II. SWITCHING PATTERN AND CONTROL OF CSBI A. Swiching Paern The Curren Source Boos Inverer (CBSI) opology is illusraed in Fig. 1 based on modified space-vecor PWM echnique, here called PPWM. A deailed descripion of he developed swiching paern is presened in [13]. 978-1-4799-4546-7/14/$31. 214 IEEE
Plan S 11 L dc P ref Conroller m α Swiching Perns S 21 S 31 S 12 V dc S w1 S w2 S w3 L f Grid S 22 S 32 S w4 S w5 S w6 Load C s P Figure 1: CSBI and is conroller configuraion LDC VDC S 1 S4 (a) L DC I DC V L Figure 2: Secors of he Proposed Swiching for CSB S1 In [18], he capabiliy of his echnique is demonsraed for conrolling he acive and reacive power, effecively. The main purpose of he swiching paern is o injec in-phase sinusoidal currens ino he hree phases of he grid, whereas he dc inducor curren is kep a consan a he desired level. In order o achieve an effecive operaion, six secions in each grid volage cycle are proposed in Fig 2, in erms of SVPWM mehod. LDC S 5 (b) v b Cs v a In each secion, here is one charging sage by keeping he swiches of he legs on o sore energy in he dc link inducor and wo discharging sages by applying he wo line-o-line volages o he oupu of he inverer o injec he sored energy ino he grid. For example, in he firs sage, charging sage will happen by urning S w1 and S w2 on and keeping ohers off. The inducor curren increases and oupu currens are supplied by C s. In he sages 2 and 3 shown in Fig. 3(b) and (c), he inducor curren discharges hrough C s in which he wo line-o-line volages V ab and V ac are applied o he inverer, respecively. Since phase a is common beween hese wo sages, his phase is used for he charging sage. The swiching paern on all secors can be found in Fig. 4 and Table I. Here c is he charging ime, d1 and d2 are he ime inervals of discharging. The relaionship of hese ime inervals gives T = + + (1) s c d1 d 2 VDC S 1 I DC (c) Figure 3: Three sages of differen swiching paerns for CSB in Sage I. (a) Sage I. (b) Sage II. (c) Sage III. These ime inervals mus saisfy he following objecives: (i) he inverer oupu curren conains minimum harmonic conens, and (ii) he dc-link inducor curren says a a fixed level. S6 v c Cs v a
Figure 4: Three sages for differen swiching Table 1. The swiching paern Secion I II III IV V VI U 1 v ab v ac v bc v ba v ca v cb U 2 v ac v bc v ba v ca v cb v ab S w1 T s d1 c d2 S w2 c d2 T s d1 S w3 d2 T s d1 c S w4 d1 c d2 T s S w5 c d2 T s d1 S w6 d2 T s d1 c As a resul, if vab = 6Vrms cos( ω ) measured as he reference signal for his mehod, he duy cycles of he wo discharging, and one charging ime inervals are compued as follows d = m cos( ω α ) (2) 1 2π d2 = m cos( ω α ) (3) 3 where d 1 = d1 /T s and d 2 = d2 /T s are he wo discharging duy cycle and d c = c /T s is he charging duy cycle, m is he modulaion index and α is he phase shif wih respec o he line-line reference volage, v ab. B. Sae-Space Averaged Modelinf of CSBI The sae-space model, considered in his sudy, is defined as x& () = Ax() + Bu() (4) y() = Cx() where, x, u and y define he saes, conrol inpus, and oupus of he sysem, while A, B and C represen he sysem marix, conrol marix and oupu marix, respecively. The large-signal sae-space-averaged model of he gridconneced single-sage boos inverer sysem can be represened in he synchronous dq-frame of reference as in (5) based on [19]. Rdc 3mcosϕ 3msinϕ 1 L 2 2 dc Ldc L dc L dc dc f dc 3m cosα q = ω s q + qs 2C d d ds 3msinϕ ωs 2C i i v d v v v d v v v The sae vecor x consiss of he sae variables of he sysem which are he independen inducor curren and capacior volages, i.e. x = [i dc, v q, v d ] T. Also, u = [v dc, v qs, v ds ] T represens he sysem inpus, while he modulaion angle, φ is assumed consan bu modulaion index, m is used o regulae he injeced acive powers o he grid. III. PRACTICAL CONTROL WITH TIME DELAY AND SOLUTION Time delay can be esimaed around a sampling period in mos DSP based conrollers, however, a DSP board can inroduce greaer ime delay and i depends on he complexiy of applicaion, parallel processors, and hreas and so on. Here in he experimenal resul and seup, a dspace muli DSP board DS114 [15] has been used. This board can be direcly programmed by MahWorks join wih Real-Time Inerface (RTI) developed by dspace using MATLAB/SIMULINK and has been conneced o a deskop compuer. The board has wo processors: firs one is a maser DSP which operaes a 25MHz and second one is a TMS32F24 microconroller operaing a 2MHz as a slave DSP. The maser DSP generaes and debugs he conrol algorihm and also monioring he daa. The slave DSP acs as a modulaor for he maser DSP [14]. In he pracical use, ime-delay exiss in he conrolling signal and also he sensing signal. For grid-conneced applicaions, he SE-inverers should be synchronizing wih grid signals. Two volage sensors will do his ask. The daa from hese wo sensors goes o Analog o Digial (A/D) (5)
Inpus/Oupus (I/O) of dspace and hen rigger SVWPM algorihm o generae he swiching signal. On he oher hand, swiching signals should be sen o SE-CS inverer using dspace D/A I/O and should be also modulaed by he slave DSP. Boh sensing and generaing swiching signals process inroduce ime-delays in he sysem. Esimaing and finding soluion for hese delays improves he sysem performance and avoids unwaned failures. Le s only assume swiching signal ime delay for now. The ime delay acquained wih dspace conroller can be calculaed by [14]: τ = Texc +.5Ts (6) whereτ is he ime delay, T exc is he execuion ime of he maser DSP and T s is he sampling period. In (6), if T exc is greaer han.5t s, he resuling ime delay is longer han one sampling cycle. In his case, if we ignore he ime delay exising in he conrol inpu (swiching signals) and feedback secion (grid volage) of he sysem, hen he dynamic performance of he sysem can be corruped and even worse be unsable and fail. Here, we focus on ime delay exising in sensing line. To overcome his problem, we simply send a sep funcion o one of he dspace D/A I/O s and ge is feedback from he A/D I/O s. As soon as, he sep funcion is deeced, he clock sops and resul divided by wo. This gives us, a real ime rack of ime delay for boh sensing signals. If his ime delay is larger han he sampling period, i should be esimaed and applied o he sysem. A buffer will be used o sore all daa received from he grid sensors for each sampling period. Also he ime delay will be calculaed based on he above echnique. As he saes are periodic, we can easily predic and esimae curren phase of he grid for all hree phases and send appropriae swiching paern o he sysem. For a ime delay on conrol inpu we can use a modified conroller as follows. Consider he sae-space model for SVPWM swiching conrol saring by (4). Here is discreized sae space model of he sysem wihou ime delay: where, Ts x( k + 1) = Gx( k) + Hu( k) y( k) = Cx( k) H = B e Aλ d λ and G = e AT s. The conrol inpu signal is designed based on he sae feedback algorihm [16]: u( k) = KI xi ( k) KPx( k) (8) where K I and K P are he inegraion and proporional gains ha can be deermined by pole-placemen mehod. Also he new sae variable x I can be calculaed from: x I ( k ) = x I ( k 1) + y r ( k ) y ( k ) (9) where y r is he reference inpu. Wih he above definiions, he following new sae space model resuls: (7) ) ) X ( k + 1) = AX( k) + Bu ˆ ( k) + Dyr ( k + 1) yk ( ) = CX ˆ ( k) where X ( k ) = x ( k ) x ( ) T I k, ˆ G A = CG I T = [ ] and D ˆ = [ I] Bˆ H CH T, C ˆ = [ C ] (1) If here is ime delay in he conrol secion, hen he equaion (4) will be convered o x& () = Ax() + Bu( τ ) (11) y() = Cx() For solving he ime-delay effec in swiching conrol signal (11), we used an observer conroller based on modificaion of he smih predicor [16, 13]. The conrol inpu signal under he ime delay effec can be found by subsiuing saes x by is prediced ˆx in (8): u( k) = K I xi ( k) K P xˆ( k) (12) and y by Cxˆ in (9): x ( k) = x ( k 1) + y ( k) Cxˆ( k) (13) I I where ˆx is he esimaed sae vecor calculaed by he observer ha predic he sae vecor x oneτ ahead of he ime. In he case haτ is larger han sampling period T s, he sae esimae can be calculaed as follows: ) xˆ( k) = Gx( k) + Hˆ ˆ 1u( k 2) + H2u( k 1) A e τ Ts τ T ˆ AT H A 1 = Be e λ d λ, ˆ s 2 where G ˆ =, 1 r H = B eaλ d λ. (14) IV. SIMULATION AND EXPERIMENTAL RESULTS The simulaion and experimenal resuls are presened in his secion o show he effeciveness of he proposed conroller based on he ime delay. The circui parameers in his simulaion have been seleced as: V dc =3 vol, C s =15 μf, L dc =12 mh, L f =2mH. The conrol secion is implemened using MATLAB Simulink in conjuncion wih dspace 114 conrol block, which is inerfaced wih he hardware. The PWM swiching frequency is se o be 3 khz and he line-oline rms volage value is 27.846 vol. Fig. 6 illusraes he experimenal resuls of inverer curren and oupu volage when he convenional conrol algorihm (wihou consideraion of ime delay) is applied. Since he waveforms of all hree phases are similar, only he curren and volage of phase A are shown. I can be seen ha he inverer curren effecively flucuaes due o he ime delay of he conroller which is no aken ino accoun. On he oher hand, as shown in Fig. 7, using proposed conrol mehod, he flucuaion in he inverer curren as well as oupu volage is properly eradicaed and he CSI operaes properly. To evaluae dynamics of he CSI, simulaion is carried ou o invesigae he response of converer oupu acive power o a sep change of reference power.
Figure 6: CSBI performance wih convenional conrol mehod Fig. 8(a) and (b) shows he simulaion of he converer curren when he acive power, P ref, has insanly changes a = 5sec from 1 o 2 was and 1 o 5, respecively. As i can be observed, he conrollers can effecively rack he acive power references wihou harming he sabiliy of he sysem. Oupu Power (Wa) Oupu Power (Wa) 11 1 22 2 18 16 14 12 1 9 8 7 6 5 Refrence value Real value 8 2 3 4 5 6 7 8 Time (s) (a) Refrence value Real value 4 2 3 4 5 6 7 8 Time (s) (b) Fig. 8. Simulaion resuls of CSBI response o sep change of acive power V. CONCLUSION In his paper, we have sudied ime-delay effec of an SVPWM based swiching paern for grid conneced hreephase curren source inverer. We have proposed an algorihm o rack he ime delay in real-ime o overcome he effec of ime-delay produced in sensing loop. This guaranees synchronizaion beween grid phase and inverer oupu. Also, we applied observer sae feedback conroller o overcome he effec of ime-delay in he conrol signal. Our experimenal resuls clearly showed ha he proposed approach can compensae he effec of ime delay and improve qualiy of oupu inverer signal. REFERENCES [1] Heydari, H.; Moghadasi, AH., "Opimizaion Scheme in Combinaorial UPQC and SFCL Using Normalized Simulaed Annealing," Power Delivery, IEEE Transacions on, vol.26, no.3, pp.1489,1498, July 211. Figure 7: CSBI performance wih proposed conrol mehod. [2] Sargolzaei, A., Jamaei, M., Yen, Kang.,Sarwa, A. Acive/Reacive Power Conrol of Three Phase Grid Conneced Curren Source Boos Inverer Using Paricle Swarm Opimizaion, 23rd Inernaional Conference on Sysems Engineering (ICSEng214). [3] Maeda, T., Masuda, Y., & Masumura, T. (1979). Curren source inverer: Google Paens. [4] Sao, S. (21). Curren source inverer: Google Paens. [5] Shen, D., & Lehn, P. (22). Modeling, analysis, and conrol of a curren source inverer-based STATCOM. Power Delivery, IEEE Transacions on, 17(1), 248-253. [6] Wang, F., & Shen, W. (29). Volage source inverer. IEEE Indusry Applicaions Magazine, 15(2). [7] Malinowski, M., Gopakumar, K., Rodriguez, J., & Perez, M. A. A survey on cascaded mulilevel inverers. Indusrial Elecronics, IEEE Transacions on, 57(7), 2197-226., 21. [8] Rodriguez, J., Lai, J.-S., & Peng, F. Z. Mulilevel inverers: a survey of opologies, conrols, and applicaions. Indusrial Elecronics, IEEE Transacions on, 49(4), 724-738., 22. [9] Kandasamy, K., &Sahoo, S. K. (213). A Review of Marix Converer and Novel Conrol Mehod of DC-AC Marix Converer. ijm, 1(3), 1. [1] Sahoo, A. K., Basu, K., & Mohan, N., Comparison of filer componens of back-o-back and marix converer by analyical esimaion of ripple quaniies. Indusrial Elecronics Sociey, IECON 213-39h Annual Conference of he IEEE., 213. [11] Vander Meulen, A., &Maurin, J. Curren source inverer vs. Volage source inverer opology Applicaion Engineers. 21. [12] Klumpner, A new single-sage curren source inverer for phoovolaic and fuel cell applicaions using reverse blocking IGBTs, Paper presened a he Power Elecronics Specialiss Conference, 27. PESC 27. IEEE. [13] Mirafzal, B., Saghaleini, M., &Kaviani, A. K. An SVPWM-based swiching paern for sand-alone and grid-conneced hree-phase singlesage boos inverers. Power Elecronics, IEEE Transacions on, 26(4), 112-1111, 211. [14] H. P., Rahman, M. F., & Granham, C. Time delay compensaion for a DSP-based curren-source converer using observer-predicor conroller, In Power Elecronics and Drive Sysems, 27. PEDS'7. 7h Inernaional Conference on (pp. 191-196). IEEE. [15] DSJ14 R&D Conroller Board - Feaure Reference: dspace GmbH, 24. [16] K. Ogaa, Discree-ime conrol sysem: Prenice HallInernaional, London, 1987. [17] The conrol handbook: CRC Press, 1996. [18] Saghaleini, M.; Mirafzal, B., "Power conrol in hree-phase gridconneced curren-source boos inverer," Energy Conversion Congress and Exposiion (ECCE), 211 IEEE, vol., no., pp.776,783, 17-22 Sep. 2. [19] Kaviani, Ali.K.; Mirafzal, Behrooz, "Sabiliy analysis of he hreephase single-sage boos inverer," Applied Power Elecronics Conference and Exposiion (APEC), 213 Tweny-Eighh Annual IEEE, vol., no., pp.918,923, 17-21,March,213.