N-channel 650 V, 0.087 Ω typ., 32 A MDmesh M2 Power MOSFET in a TO-247 package Datasheet - production data Features Order code V DS R DS(on) max. I D STW40N65M2 650 V 0.099 Ω 32 A TO-247 1 3 2 Extremely low gate charge Excellent output capacitance (C OSS ) profile 100% avalanche tested Zener-protected Applications Switching applications Figure 1: Internal schematic diagram Description This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packaging STW40N65M2 40N65M2 TO-247 Tube February 2015 DocID027443 Rev 1 1/12 This is information on a product in full production. www.st.com
Contents STW40N65M2 Contents 1 Electrical ratings... 3 2 Electrical characteristics... 4 2.2 Electrical characteristics (curves)... 6 3 Test circuits... 8 4 Package information... 9 4.1 TO-247 package information... 9 5 Revision history... 11 2/12 DocID027443 Rev 1
Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 25 V I D Drain current (continuous) at T C = 25 C 32 A I D Drain current (continuous) at T C= 100 C 20 A I DM (1) Drain current (pulsed) 128 A P TOT Total dissipation at T C = 25 C 250 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns T stg Storage temperature - 55 to 150 T j Max. operating junction temperature 150 Notes: (1) Pulse width limited by safe operating area. (2) ISD 32 A, di/dt 400 A/µs; V DS peak < V (BR)DSS, V DD = 400 V (3) VDS 520 V C Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 0.5 C/W R thj-amb Thermal resistance junction-ambient max 50 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) Single pulse avalanche energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 3 A 820 mj DocID027443 Rev 1 3/12
Electrical characteristics STW40N65M2 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 5: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage Drain current V GS = 0 V, I D = 1 ma 650 V V GS = 0 V, V DS = 650 V 1 µa V GS = 0 V, V DS = 650 V, T C = 125 C 100 µa I GSS Gate-body leakage current V DS = 0 V, V GS = ± 25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa 2 3 4 V R DS(on) Static drain-source onresistance V GS = 10 V, I D = 16 A 0.087 0.099 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance - 2355 - pf C oss Output capacitance V DS= 100 V, f = 1 MHz, - 102 - pf V GS = 0 V Reverse transfer C rss - 2.7 - pf capacitance Equivalent output capacitance V DS = 0 V to 520 V, V GS = 0 V - 380 - pf R G Intrinsic gate resistance f = 1 MHz open drain - 4.5 - Ω C oss eq. (1) Q g Total gate charge V DD = 520 V, I D = 32 A, - 56.5 - nc Q gs Gate-source charge V GS = 10 V (see Figure 15: - 8 - nc Q gd Gate-drain charge "Gate charge test circuit") - 24 - nc Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 325 V, I D = 16 A - 15 - ns t r Rise time R G = 4.7 Ω, V GS = 10 V (see Figure 14: "Switching times - 10 - ns t d(off) Turn-off-delay time test circuit for resistive load" - 96.5 - ns t f Fall time and Figure 19: "Switching time waveform") - 12 - ns 4/12 DocID027443 Rev 1
Table 8: Source drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD I SDM (1) V SD (2) t rr Q rr I RRM t rr Q rr I RRM Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current - 32 A - 128 A V GS = 0 V, I SD = 32 A - 1.6 V I SD = 32 A, di/dt = 100 A/µs, V DD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") I SD = 32 A, di/dt = 100 A/µs, V DD = 60 V, T j = 150 C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Notes: (1) Pulse width is limited by safe operating area (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5% - 468 ns - 8.7 µc - 37.5 A - 610 ns - 11.7 µc - 39 A DocID027443 Rev 1 5/12
Electrical characteristics 2.2 Electrical characteristics (curves) Figure 2: Safe operating area I D GIPD030220151540ALS (A) STW40N65M2 Figure 3: Thermal impedance GC18460 K δ=0.5 100 10 1 Operation in this area is limited by max R DS(on) T j = 150 C T c = 25 C Single pulse 0.1 0.1 1 10 100 10µs 100µs 1ms 10ms V DS (V) 0.1 10-1 0.05 10-2 0.2 0.02 0.01 Single pulse Z th = K*R thj-c δ= t p /Ƭ t p Ƭ 10-3 10-4 10-5 10-3 10-2 10-1 t p (s) I D (A) 70 60 Figure 4: Output characteristics V GS = 6,7,8,9,10 V GIPG300120151500ALS V = 5 V GS Figure 5: Transfer characteristics I D (A) 70 60 GIPG300120151715ALS 50 40 30 V GS = 4 V 20 10 0 0 4 8 12 16 20 24 V (V) DS 50 V GS = 20 V 40 30 20 10 0 0 2 4 6 8 V GS (V) Figure 6: Normalized gate threshold voltage vs temperature Figure 7: Normalized V (BR)DSS vs temperature 6/12 DocID027443 Rev 1
Figure 8: Static drain-source on-resistance Electrical characteristics Figure 9: Normalized on-resistance vs. temperature Figure 10: Gate charge vs. gate-source voltage Figure 11: Capacitance variations Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID027443 Rev 1 7/12
Test circuits STW40N65M2 3 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit VDD 12 V 47 k Ω 1 kω 100 nf Vi V GS I G = CONST 100 Ω D.U.T. 2200 μ F 2.7 k Ω VG 47 k Ω PW 1 kω AM01469v1 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit G A D D.U.T. A FAST DIODE A L=100 µh 25Ω S B B B D 3.3 1000 µf µf VDD G D.U.T. RG S AM01470v1 Figure 18: Unclamped inductive waveform V (B R)DS S Figure 19: Switching time waveform t on toff t d(on) t r t d(off) t f V D 90% 90% I DM 10% I D 0 10% V DS V DD V DD V GS 90% AM01472v1 0 10% AM01473v1 8/12 DocID027443 Rev 1
Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-247 package information Figure 20: TO-247 drawing 0075325_H DocID027443 Rev 1 9/12
Package information STW40N65M2 Table 9: TO-247 mechanical data mm. Dim. Min. Typ. Max. A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 D 19.85 20.15 E 15.45 15.75 e 5.30 5.45 5.60 L 14.20 14.80 L1 3.70 4.30 L2 18.50 ØP 3.55 3.65 ØR 4.50 5.50 S 5.30 5.50 5.70 10/12 DocID027443 Rev 1
Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 09-Feb-2014 1 First release. DocID027443 Rev 1 11/12
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