LSI Logic LSI53C13 PCI-X to Dual Channel Ultra32 SCSI Controller.18 µm CMOS Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 5, Ottawa, ON K2H 5B7, Canada Tel: 613.829.414 Fax: 613.829.515 www.chipworks.com
LSI Logic LSI53C13 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Overview 3.1 Selected Package Analysis 4 Process 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Logic Transistors and Poly 4.7 Isolation 4.8 Wells and Substrate 5 SRAM Cell Analysis 5.1 Memory Cell Overview 5.2 6T SRAM (SRAM A) Analysis 5.3 SRAM B 6 Materials Analysis 6.1 Materials Analysis Overview 6.2 SEM-EDS Analysis of Package Metals 6.3 TEM-EDS Analysis of Dielectrics 6.4 TEM-EDS Analysis of Metals and Transistors
LSI Logic LSI53C13 Structural Analysis 7 Critical Dimensions 7.1 Package Vertical Dimensions 7.2 Measured Dielectric Thicknesses 7.3 Metallization Vertical and Horizontal Dimensions 7.4 Via and Contact Horizontal Dimensions 7.5 Transistor and Poly Measured Dimensions 7.6 Isolation Measured Dimensions 7.7 Well and Substrate Dimensions 7.8 SRAM A Measured Dimensions 7.9 SRAM B Measured Dimensions 8 Statement of Measurement Uncertainty and Scope Variation 9 References Report Evaluation
LSI Logic LSI53C13 Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Plan View Package X-Ray 2.1.4 Die Photograph 2.1.5 Die Markings 2.1.6 Metal 1 Die Photograph 2.1.7 Analysis Sites 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Bond Pad Overview 2.2.6 Detail of Bond Pads 3 Package Overview 3.1.1 Package Cross Section Overview 3.1.2 Die, Mold Compound, and PCB 3.1.3 Through Hole Via and Solder Ball 3.1.4 PCB Metal and Dielectric Thicknesses 3.1.5 Package Lands 3.1.6 Stitch Bond Overview 3.1.7 Detail of Stitch Bond and Land Platings 3.1.8 Solder Ball Land 3.1.9 Detail of Solder Ball Land Platings 3.1.1 Die Thickness 3.1.11 Die Edge and Die Seal 3.1.12 Au Ball Bond 4 Process 4.1.1 General Structure 4.1.2 Die Seal 4.2.1 Bond Pad Overview 4.2.2 Bond Pad Edge 4.3.1 Passivation 4.3.2 Passivation Composition TEM 4.3.3 IMD 4 4.3.4 IMD 4 TEM 4.3.5 IMD 3 4.3.6 IMD 2 4.3.7 IMD 1 4.3.8 PMD 4.3.9 PMD 3 Sub Layers
LSI Logic LSI53C13 Overview 1-2 4.4.1 Minimum Pitch Metal 5 4.4.2 Metal 5 Cap TEM 4.4.3 Metal 5 Barrier TEM 4.4.4 Minimum Pitch Metal 4 4.4.5 Metal 4 Cap TEM 4.4.6 Metal 4 Barrier TEM 4.4.7 Minimum Pitch Metal 3 4.4.8 Metal 3 Cap TEM 4.4.9 Metal 3 Barrier TEM 4.4.1 Minimum Pitch Metal 2 4.4.11 Metal 2 Composition TEM 4.4.12 Metal 2 Cap TEM 4.4.13 Metal 2 Barrier TEM 4.4.14 Minimum Pitch Metal 1 4.4.15 Metal 1 Composition TEM 4.4.16 Metal 1 Cap TEM 4.4.17 Metal 1 Barrier TEM 4.4.18 Minimum Pitch Metal 4.4.19 Metal Overview TEM 4.5.1 Minimum Pitch Via 4s 4.5.2 Minimum Pitch Via 3s 4.5.3 Minimum Pitch Via 2s 4.5.4 Detail of Via 2 TEM 4.5.5 Minimum Pitch Via 1a 4.5.6 Minimum Pitch Contacts to Metal 4.5.7 Detail of Contact to Metal 4.5.8 Contact TiN Thickness TEM 4.5.9 Contact to Poly TEM 4.5.1 Contact to Diffusion Interface TEM 4.6.1 Minimum Gate Length NMOS Logic Transistors 4.6.2 Minimum Gate Length PMOS Logic Transistors 4.6.3 Minimum Pitch Poly 4.6.4 Logic MOS Transistor S/D Contacts TEM 4.6.5 MOS Transistor Gate and S/D Silicide TEM 4.6.6 Detail of MOS Transistor Gate TEM 4.6.7 Detail of Gate SWS Region TEM 4.6.8 TEM Gate Oxide TEM 4.7.1 Minimum Width STI 4.7.2 Step in STI Metal Trench Etch 4.7.3 Poly Over STI Gate Wrap 4.7.4 Gate Wrap TEM 4.8.1 SCM Overview of N and P-wells 4.8.2 Detailed SCM of N and P-Wells 4.8.3 SRP of P-well and Substrate Doping 4.8.4 Detailed SRP of P-well
LSI Logic LSI53C13 Overview 1-3 5 SRAM Cell Analysis 5.2.1 SRAM A Cell Schematic 5.2.2 SRAM A Metal 3 5.2.3 SRAM A Metal 2 5.2.4 SRAM A Metal 1 5.2.5 SRAM A Poly/Metal 5.2.6 SRAM A Diffusion 5.2.7 SRAM A NMOS Pull Down Transistor Gate Length (T4, T5) 5.2.8 Detail of SRAM A NMOS Pull Down Transistor Gate Length (T4, T5) 5.2.9 SRAM A NMOS Pull Down Transistor Gate Length (TEM) 5.2.1 SRAM A PMOS Pull Up Transistor Gate Length (T3, T6) 5.2.11 SRAM A PMOS Pull Up Transistor Gate Length (T3, T6) 5.2.12 SRAM A NMOS Access Transistor Gate Width (T2) 5.2.13 SRAM A NMOS Access Transistor Gate Width (T2) 5.2.14 SRAM A NMOS Pull Down and PMOS Pull Up Gate Widths (T3, T4) 5.3.1 SRAM B Cell Schematic 5.3.2 SRAM B Metal 3 5.3.3 SRAM B Metal 2 5.3.4 SRAM B Metal 1 5.3.5 SRAM B Poly/Metal 5.3.6 SRAM B Diffusion 5.3.7 SRAM B NMOS Pull Down and Access Transistor Gate Length (T2, T6) 5.3.8 SRAM B Detail of NMOS Pull Down and Access Transistor Gate Length (T2, T6) 5.3.9 SRAM B PMOS Pull Up Transistor Gate Length (T4) 5.3.1 SRAM B NMOS Access Transistor Gate Length (T8) 6 Materials Analysis 6.2.1 SEM-EDS Spectra of Package Metals 6.3.1 TEM-EDS Spectra of Passivation 6.3.2 TEM-EDS Spectra of IMD 4 6.3.3 TEM-EDS Spectra of IMD 3 6.3.4 TEM-EDS Spectra of IMD 2 6.3.5 TEM-EDS Spectra of IMD 1 6.3.6 TEM-EDS Spectra of PMD 6.3.7 TEM-EDS Spectrum of STI 6.4.1 TEM-EDS Spectra of Metal 1 Cap 6.4.2 TEM-EDS Spectrum of Gate Silicide 6.4.3 TEM-EDS Spectrum of S/D Silicide
LSI Logic LSI53C13 Overview 1-4 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 3 Package Overview 3.1.1 Package Measured Vertical Dimensions 4 Process 4.3.1 Measured Dielectric Thicknesses 4.4.1 Metallization Measured Vertical Dimensions 4.4.2 Metallization Measured Horizontal Dimensions 4.5.1 Via and Contact Minimum Observed Horizontal Dimensions 4.6.1 Peripheral Transistor Horizontal Dimensions 4.6.2 Peripheral Transistor and Polycide Vertical Dimensions 4.7.1 STI Measured Dimensions 4.8.1 Measured Well Depths and Die Thickness 5 SRAM Cell Analysis 5.2.1 SRAM A Measured Dimensions 5.3.1 SRAM B Measured Dimensions 7 Critical Dimensions 7.1.1 Package Measured Vertical Dimensions 7.2.1 Measured Dielectric Thicknesses 7.3.1 Metallization Measured Vertical Dimensions 7.3.2 Metallization Measured Horizontal Dimensions 7.4.1 Via and Contact Minimum Observed Horizontal Dimensions 7.5.1 Peripheral Transistor Horizontal Dimensions 7.5.2 Peripheral Transistor and Polycide Vertical Dimensions 7.6.1 STI Measured Dimensions 7.7.1 Measured Well Depths and Die Thickness 7.8.1 SRAM A Measured Dimensions 7.9.1 SRAM B Measured Dimensions
About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 5 Ottawa, Ontario K2H 5B7 Canada T: 1.613.829.414 F: 1.613.829.515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com