Nonlinear Characterization and Modeling Through Pulsed IV/S-Parameters

OUTLINE Introduction Core device model extraction Model Enhancement Model Validation

Types of Large-Signal Transistor Models Convergence Operating range Physic model Compact model Behavioral model Extrapolation Accuracy Physical insight Easy modeling process Usability for Circuit design

Commercial compact FET models Mostly used models for GaN HEMTs FET models Number of parameters Electro-thermal effect Trapping Effects Original Device Context Curtice3 [1] 59 No No GaAs FET CFET [2] 53 Yes No HEMT EEHEMT1 [3] 71 No No HEMT Angelov [4] 80 Yes No HEMT/MESFET AMCAD HEMT1 [5] 65 Yes Yes GaN HEMT AMCAD GaN HEMT1 is the only model here with a complete extraction flow based on pulsed IV/RF measurements

Rs, Rd Idss Compact FET model extraction flow 1.6 1.4 Rd y = 0.0049x + 0.6889 1.2 1 Rs 0.8 y = 0.0029x + 0.6375 0.6 0.4 0 50 100 150 200 T C 1.18 1.16 1.14 y = -0.0008x + 1.1543 1.12 1.1 1.08 1.06 1.04 1.02 0 50 100 150 200 T C Small-Signal IV Model Non-linear capacitances Thermal model Trapping effects Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Dgs=f(Vgs) Dgd=f(Vgd) Ids=f(Vgs,Vds) Cgs=f(Vgs) Cgd=f(Vgd) Dgs=f(Vgs,T) Dgd=f(Vgd,T) Ids=f(Vgs,Vds,T) Rs=f(T) Rd=f(T) Ids=f(Vgs_trap,Vds,T) Various effects are successively added

Parameter extraction methodology

OUTLINE Introduction Core device model extraction Model Enhancement Model Validation

Parameter extraction methodology Core device model Pulsed IV / S parameter Measurements 1 st step: bias-dependant S parameters Multibias set of linear models 2 nd step: large signal fitting Modeling Nonlinear model

Pulsed IV measurements Short pulse : Quasi-isothermal conditions Low duty cycle : Constant mean temperature Quiescent bias point : Thermal conditions fixed Several quiescent bias point

Compact FET model extraction flow Small-Signal Modelling Process Pulsed S parameter measurements Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Bias Bias

Pulsed S parameter measurements The first & most important point : Pulsed S parameter measurements must not be noisy Small S2P measurement variation = strong influence over the linear model extraction : optimization algorithm Requirements : IVCAD Dynamic range in pulsed mode > 90dB for Duty Cycle ~ 5%

Pulsed S-parameter Measurements Pulsed S-parameter measurements must not be noisy at low duty cycle with narrow pulse width Pulse detection methods Wideband detection Narrowband detection Receiver samples IF filter Receiver samples IF filter No pulse desensitization Increased noise with narrow pulse width due to wider IF bandwidth Limited pulse width by maximum available IF bandwidth Narrower minimum pulse width than wideband pulse Reduced dynamic range with low duty cycle due to pulse desensitization by 20*log(duty cycle)

PNA/PNA-X Noise reduction techniques and performances Peak-to-peak noise with wideband detection at 10% duty cycle No averaging in calibration and measurements 0.03 db 0.04 db 0.06 db 0.09 db Pulse width (IFBW) 10 us (150 khz) 5 us (280 khz) 1 us (1.5 MHz) 500 ns (3 MHz) Averaging 20 times in calibration and measurements 0.005 db 0.006 db 0.012 db 0.013 db

PNA/PNA-X Noise reduction techniques and performances Dynamic range with wideband detection at 10% duty cycle with 10 us, 5 us, 1 us, 500 ns pulse width No averaging in calibration and measurements, 1% smoothing on Averaging 20 times in calibration and measurements, 1% smoothing on

PNA/PNA-X Noise reduction techniques and performances Peak-to-peak noise at 10% duty cycle Wideband detection with 20 times averaging in calibration and measurements Narrowband detection with no averaging in calibration and measurements Pulse width 0.005 db 0.006 db 0.012 db 0.013 db 10 us 5 us 1 us 500 ns 0.009 db 0.009 db 0.012 db 0.011 db

PNA/PNA-X Noise reduction techniques and performances Dynamic range with narrowband detection at 500 ns pulse width Hardware gating No Averaging, 1% smoothing on, 500 Hz IF bandwidth Crystal filter Software gating >100 db at 10% >100 db at 5% 90 db at 1% 85 db at 0.5% Spectral nulling

E836x Legacy PNA N524xA PNA-X N522xA New PNA Pulse generator External Internal/External Internal/External Pulse modulator External Internal/External Internal/External Wideband detection Max BW/Min PW 35 khz / 50 us 15 MHz / 100 ns 15 MHz / 100 ns High level noise* 0.006 dbrms 0.002 dbrms 0.002 to 0.003 dbrms Dynamic range** 114 to 123 db 124 to 129 db 127 db Narrowband detection Min IF gate width 20 ns <20 ns <20 ns Dynamic range*** 85 db <105 db <105 db * Specified as trace noise magnitude, at 20 GHz, at 1 khz IF bandwidth ** Specified performance at 20 GHz, at 10 Hz IF bandwidth *** Measured performance at 10 GHz at 10 Hz IF bandwidth, 1% duty cycle

Compact FET model extraction flow Small-Signal IV Model Rg Lg Cpg Ls Cpd Ld Rs Rd Ri Cds τ Gm Gd Cgs Cgd Rgd Dgs=f(Vgs) Dgd=f(Vgd) Ids=f(Vgs,Vds) RF DC DC RF

Pulsed IV parameter measurements Pulsed IV measurements must be accurate from low to high voltage/current values Accurate IV data = Reliable current source Transconductance Leakage current Ideality factor schottky diode IVCAD

How to get accurate pulsed IV measurements? PIV system Pulsed IV parameter measurements

Pulsed IV parameter measurements How to get accurate pulsed IV measurements? +15V Gate 15 bits + sign Drain 250V 16 bits 15 bits + sign -15V 25V 16 bits Pulse shape monitoring 20ns time resolution

Pulsed IV parameter measurements How to get accurate pulsed IV measurements? 200mA 9µA 400µA 200mA 20mA 0mA 1µA 40µA 20mA -15V 0,6mV 65mV 15V 0V Measurement Resolution Voltage Absolute Accuracy Voltage Range

How to get accurate pulsed IV measurements? 10A Pulsed IV parameter measurements 200µA 20mA 1A 0A 22µA 2mA Measurement Resolution Voltage Absolute Accuracy Voltage Range 0,53mV 4,9mV 50mV 500mV 0V 25V 250V

Pulsed IV & S parameter measurements How to get accurate pulsed IV measurements? Synchronisation between Pulse IV and pulse S parameters

Pulsed S parameter measurements How to get accurate pulsed IV measurements? Synchronisation between Pulse IV and pulse S parameters

ignal model presents Small signal FET modeling circuit c circuit related to the ments Cpg Extrinsic parameters - pad capacitances Cpg, Cpd - port metallisation inductances Lg, Ld, Ls - port ohmic resistances Rg, Rd, Rs developped at the allows to optimize the ments in order to get ameters that do not he frequency Intrinsic parameters - channel capacitances Cgs, Cgd - voltage-controlled current source with transconductance gm and transit time delay tau - ohmic resistances Ri, Rgd - output capacitance Cds and resistance Rds G Lg Rg Rd Ld Transistor intrinsic intrinsèque transistor Cpd Rs Ls S Grille Gate Cgd Cgs Ri Transistor intrinsic intrinsèque transistor D Rgd Gm Source Drain Rds Cds Gm = Gm 0 e -j

Small signal FET modeling Extraction of extrinsic and intrinsic parameters: There is only one set of extrinsic parameters for which intrinsic parameters are independent from the frequency For a given set of extrinsic parameters, intrinsic admittance matrix of the device is extracted from measured [S] parameters No Set min. and max. for each extrinsic parameter - user choice - initiated by cold FET meas. Optimization algorithm: annealing, fast simulated diffusion (intrinsic parameters calculus) Fit? Yes Multi-biasing extraction of the linear model

OUTLINE Introduction Core device model extraction Model Enhancement Model Validation

Parameter extraction methodology Core device model Pulsed IV / S parameter measurement results 1 st step: bias-dependant S parameters Multibias set of linear models 2 nd step: large signal fitting Nonlinear model Model Enhancement Specific measurements - diodes - g-d breakdown - thermal effects - charge carrier trapping 3 rd step: setting of additional parameters Enhanced Nonlinear model

Non linear capacitances Gate charge is partitioned into gate source and gate-drain charge. Each charge expression is a function of both VDS and VGS. For power amplifier applications, 2D models do not bring a breakthrough in the precision, but they are much more complex 1 dimension capacitances extracted along optimal load-line are preferred due to simplicity. 1D capacitances with equations based on hyperbolic tangents are naturally charge conservatives Output Capacitance Cds is linear no voltage dependence (weak anyway) Cgd=f(Vgd) Cgs=f(Vgs) + Modeling simplicity. Very good convergence - Validity of the 1D? 33

Capacitances modeling: 1D vs 2D Non linear capacitances Better fit of the 2D model in wider domain But the 1D model has a good behavior 34

Non linear capacitances Cgd Feedback capacitance Cgd is a strong function of drain voltage. Cgd capacitance extracted along optimal load-line for power amplification

Non linear capacitances Cgs Input capacitance Cgs is a strong function of gate voltage. The gate-voltage non-linearity also effects model s harmonic generation Cgs capacitance extracted along optimal load-line for power amplification

Gm (S) Id (A) Output current source 0.6 0.4 meas. model 0.2 0.0 0 10 20 30 40 50 60 70 Vds (V) AMCAD drain current model formulation allows to predict very accurately the I-V curves, the partial derivatives gm and gd, the knee voltage and the transconductance decrease at high current. 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00-10 -9-8 -7-6 -5-4 -3-2 -1 0 1 2 Vgs (V)

Output current source Idss amplitude Vdsp, A slope P gd M, P fitting parameters Vp0 pinch-off AlphaGm, Vgm, BetaGm, Vdm gm (derivative)

Diodes Gate-drain and gate-source diode equations include forward conduction of gate current ID Is. e Alpha.Vd (a classical formulatio n)

Ids (ma) Igs (ma) Breakdown generator Gate-drain Breakdown generator The breakdown phenomena leads to a current from the drain to the gate when the device is pinched-off and for high values of Vds voltage. In this case, the whole 800 negative current characterized on the gate is seen in positive on the drain 200 600 100 400 0 200-100 0-200 -200 0 50 100 150 200 250 Vds (V) -300 0 50 100 150 200 250 Vds (V) A polynomial expression with order 4 is necessary to model the cross of breakdown curves, with varies depending on the process

Ids (A) Ids (A) Ids (A) Ids (A) Static and Dynamic self-heating effects Thermal effects Temperature dependence with ambient or chuck temperature 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0-0.1 1.0 0.8-40 C 0 5 10 15 20 25 30 35 40 45 Vds (V) 1.0 0.8 0.6 0.4 0.2-0.0-0.2 Static 25 C 0 5 10 15 20 25 30 35 40 45 Vds (V) 0.5 0.4 0.3 0.2 0.1 0.0-0.1 1 150 C 0 5 10 15 20 25 30 35 40 45 Vds (V) 0.6 0.4 2 Dynamic 0.2-0.0-0.2 0 20 40 60 80 100 Vds (V)

Thermal effects

Thermal effects Thermal impedance extraction by simulation

Thermal effects Thermal impedance extraction by measurements

Thermal effects Drain current is only temperature dependent model element Takes into account ambient temperature and self-heating effects Thermal analog circuit to model self-heating and elevated heat sink temperatures Gate access Drain access RC cells AMCAD original current source Diodes Non linear Capacitances Breakdown source Source access Dissipated Power Thermal circuit Extrinsics

Vgs_int Trapping effects Charging and discharging of traps has influence Lg Rg on Ids and leads to current collapse. This is Cgd Rgd described in the model by trapping effects modifying the gate command and separated into gate and drain lag sub-circuits Cpg Vgs Vds Ibk Igd(T ) Gate access Drain access Cgs Igs(T ) Gate- & Drain-lag Ri AMCAD original current source Diodes Non linear Capacitances Breakdown source Source access Dissipated Power Thermal circuit Extrinsics Transistor intrinsèque Rs(T ) Ls

Trapping effects

Charge of the capacitance = Ionized traps Trapping effects Charge through Rcapture, Emission through Rémission R Rcapture Diode diode C C8 signal reshaping circuit Port Vout Port Vin R Remission Diode = dissymmetry of the capture and emission process Tuning of the magnitude of the trapping effects Fundamental assumption : dissymetry of the capture and emission process

Ids (A) (H) Trapping effects Bias dependant gate lag -> current reduction over the entire characteristic Bias dependent drain lag -> current reduction and shifts the knee-voltage to a higher Vds Model covers knee walkout to avoid errors in calculation of output power. 0.7 0.6 0.5 gate-lag : Id => Pout H 0.4 drain-lag : Id Vknee => Pout 0.3 0.2 0.1 0.0-0.1 0 5 10 15 20 25 30 35 40 45 50 55 60 Vds (V)

Ids (A) (H) Ids (A) (H) (H) Ids Ids (A) (A) (H) (H) (H) Ids (A) Pout W (H) Pout W (H) (H) Pout Pout Pout W W (H) (W) (H) (H) Trapping effects Decreasing form of the mean output current only reproduced with traps modeled 0.35 0.30 meas model without traps model model with traps model H 44 33 Pout H 0.25 Ids 0.20 0.15-10 -5-5 00 55 10 10 15 15 20 20 25 25 30 30 Pin( dbm) 22 meas 11 model without traps model model with traps model 00 0.00 0.00 0.05 0.05 0.10 0.10 0.15 0.15 0.20 0.20 0.25 0.25 0.30 0.30 0.35 0.35 Pin (W)

OUTLINE Introduction Core device model extraction Model Enhancement Model Validation

Parameter extraction methodology Core device model Pulsed IV / S parameter measurement results Model Enhancement Specific measurements Model Validation Power measurements 1 st step: bias-dependant S parameters Multibias set of linear models 2 nd step: large signal fitting - diodes - g-d breakdown - thermal effects - charge carrier trapping 3 rd step: setting of additional parameters 4 th step: implementation in commercial simulator -load-pull measurements CW, pulsed 2-tones time domain 5 th step: validation and refinement Nonlinear model Enhanced Nonlinear model Final Nonlinear model

Pout (dbm) and Gain (db) Pout (dbm) and Gain (db) Large-signal Model validation Model validation of a 8x75 µm GaN HEMT with load-pull measurements performed at 6 GHz for optimum PAE load impedance in class-ab Model validation of a 8x400 µm GaN HEMT with load-pull measurements performed at 3 GHz for the optimum Pout load impedance in class-b 40 35 30 25 20 15 10 meas. model Pout PAE gain 40 30 20 10 PAE (%) 60 40 20 0 meas. model Pout gain PAE 60 40 20 0 PAE (%) 5-10 -5 0 5 10 15 20 25 30 Pin dbm 0-20 -5 0 5 10 15 20 25 30 Pin dbm -20

Model validation VNA Based load pull system is preferred for model validation Specific Architecture DC or pulse DC supplies + meas Units PA Gate T Low loss directional couplers DUT Drain T 50 Tuner f0 VNA Tuner f0, 2f0, 3f0 CW or pulse RF signal f0 or f1+f2

Model validation VNA Based load pull system is preferred for model validation

Power meter based system are wideband measurement system f0 2.f0 3.f0 VNA based system can be narrowband measurement system f0 f0 f0 2.f0 3.f0 2.f0 3.f0 2.f0 3.f0 More information for model validation or efficient design

VNA based Load Pull systems Some Measurement definition P_in: Power delivered to the DUT by the source P_out: Power delivered to the load impedance Power gain is the ratio of the power delivered to the load (P out ) to the power delivered to the transistor by the source (P in ).

Large signal impact - class AB, 25V, 10 GHz Comparison with measurements With non optimal loads : Time domain load pull measurements Deembedding in the intrinsic reference plane Parasitic extrinsic elements must be accurately extracted by previous S parameter measurements

Testing Model Validity with Pulsed IV Simulations (Using Agilent ADS) Is your FET model suitable for high-frequency design? Is dynamic behavior included? Is it well-fitted for high-frequency, large signals? What is the model s valid range of use? Accounting for Dynamic Behavior in FET Device Models, Microwave Journal, July, 2011: http://cp.literature.agilent.com/litweb/pdf/5990-8706en.pdf Download the Pulsed IV Curve Simulation DesignGuide for FETs: http://edocs.soco.agilent.com/display/eesofkcads/pulsed+iv+curve+si mulation+designguide+for+fets

Maury Agilent AMCAD Solution

Microwave Journal March 2012 Technical Feature Compact Transistor Models: The Roadmap to First-Pass Amplifier Design Success

Hiro Maehara Applications Expert Agilent Technologies hiroyuki_maehara@agilent.com Tony Gasseling General Manager AMCAD Engineering gasseling@amcad-engineering.fr Steve Dudkiewicz Director, Business Development Maury Microwave sdudkiewicz@maurymw.com