MOSFET Parasitic Elements Three MITs of the ay Components of the source resistance and their influence on g m and R d Gate-induced drain leakage (GIL) and its effect on lowest possible leakage current Turn-on conditions of the parasitic BJTs within a single MOSFET and between the substrate and well implant Chapter 5 1
Parasitic Elements in MOSFET Parasitic elements in MOSFET resistance (performance degradation caused by source/drain resistance, poly-gate resistance, substrate resistance, etc.) capacitance (intrinsic and structural) diode (leakage, tunneling) BJT (current snap, latchup, etc.) Source/drain resistance is a major concern for submicron CMOS silicide metal contact current lines R co R sp R acc R sh spacer dielectric fringing fields gate source barrier accumulation Chapter 5 2
Critical Influence of Source Resistance V Source/drain parasitic resistance R s R co + R sh + R sp + R acc, which are contact resistance, sheet resistance, spreading resistance and accumulation resistance. R sp and R acc are functions of the gate bias and choice of the spacer material. The spacer material will also affect the source barrier through fringing fields, C GS /C G and hotcarrier effects by fringing drain field. Choice of spacer materials needs to consider all these effects and is highly tailored. If S/ resistance is large, the intrinsic MOSFET will lose its nearly ideal property where an ON/OFF switch is controlled by the gate. Effect of R S and R : usually R S is much more important since it degrades the transconductance (g m ) much more than R. GS g' V GS I R S V V I ( R + R ) S I ' BS g S V ' m V I R d GS S I V ' I g m VGS 1+ RS g m I g d Chapter 5 3 d VS 1 + ( RS + R ) g d S S g g m
R R R sp sh co Source Resistance esign Considerations 2ρ j x ln 0.75 πw x Lspacer ρsd W ρ c W ρ sd j c coth l c ρsd ρ Short-contact limit (l c <<(ρ c /ρ sd ) 1/2 ) ρc Rco Wlc Long-contact limit (l c >>(ρ c /ρ sd ) 1/2 ) R co ρ sd W ρ 2φ B ρc exp qh c * m ε siε0 N c φ B : Schottky barrier l c L spacer L ov L eff current lines R co R sh R sp R acc Chapter 5 4 x j Taur & Ning 5.2.1 ρ j : bulk resistivity (Ωcm) ρ sd : sheet resistivity (Ω/ ) ρ c : contact resistivity (Ωcm 2 ) gate accumulation x c
MOSFET Parasitic Capacitance Quasi-static intrinsic and parasitic capacitive components: (modified Meyer s capacitance for MOSFET) ideal subthreshold linear saturation C gs C ov +C spacer +C if WC ox L eff /2 WC ox L eff η C gd C ov +C spacer +C if WC ox L eff /2 C ov +C spacer +C if (much smaller) C C C ov if ε spacer ox ε0wl t ox 2ε ov spacer 2ε siε0w π π ε W 0 ln 1 + ln 1 + x 2t j ox t gate t ox x j current lines C spacer C ov gate C if (interior fringe) Chapter 5 5
Parasitic diodes MOS Parasitic iodes Junction diode leakage current is wasted since it does not participate in any transistor actions. The easy way to reduce reverse saturation current of n + -p diode is to raise the doping on the p side (substrate) before the Zener tunneling starts dominating. This put a limit to highest substrate doping around S/ junctions to be around 10 18 cm -3, or games in S/ doping profiles need to be employed. One special case of Zener tunneling current leakage: gate-induced drain leakage (GIL), where the n + side of the Zener diode is the drain, and the p + side is formed by accumulation in the channel (gate induced). This induced Zener diode is reverse-biased by V S. Therefore, the leakage happens at V GS below threshold and some significant V S. GIL Zener diode logi S/ junctioin diode V GS Chapter 5 6
GIL Leakage in MOSFET Zener tunneling E C E Fp E V Zener tunneling (or band-to-band tunneling) V A E Fn When the hole surface concentration is very large (Fermi level very close to the valence band), the valence-band electrons can tunnel through the thin barriers directly (the p-side is induced instead of by doping as in a genuine Zener diode). Sometime an Esaki signature of negative differential resistance can be measured. J b b * 3 * 2m q FV 4 2m E A exp 3 2 4π h E 3qFh gap 3/ 2 gap V A here is determined by both V GS and V S Chapter 5 7
MOSFET Hot Carrier Effects After the carrier obtains enough energy for oxide barrier, a re-directing scattering needs to happen and the vertical field needs to be in the preferred direction for carrier to get over oxide impact ionization substrate current drain junction usually has the highest electric field in abovethreshold saturation region The substrate current is caused by the hole current (in NMOSFET) from the impact ionization. The reverse-biased junction will sweep holes to substrate and electrons to drain. The gate current will be tiny, since in the pinchoff region where the carrier can get hot, the vertical field is no longer in the direction of pushing carriers toward oxide. This is good news for the sense of gate leakage current, but bad news for EEPROM programming by hot-carrier injection. Chapter 5 8
Inhomogeneous Fields along the Channel In the linear (triode) IV region, there is no pinchoff region, and the parallel field can be estimated by V S /L eff. In the saturation IV region, most of the V S drops at the pinchoff box (whether it is caused by channel potential or velocity saturation). The electric field in the pinchoff box can be very high and creates significant amount of hot and lucky carriers for impact ionization or gate current. MOSFET I sub has a typical bell shape if plotted against V GS with fixed V S, the initial increase comes from the increase in channel current (hence more carrier supply for impact ionization). The drop in large V GS is caused a big reduction in F y. F y I sub saturation linear fixed V S L eff less initializing channel carriers y Reduction of F y V GS Chapter 5 9
Parasitic BJT MOSFET Parasitic BJT first type: built-in BJT in a single bulk-type MOSFET with source as emitter, drain as collector and substrate as base. L B L eff. For normal operations, the substrate for nmosfet is tied to the lowest potential, so the parasitic BJT should be in cutoff mode. Two conditions for large I C of parasitic BJT (once this happens, the gate loses control, and MOSFET behavior is overshadowed by the BJT): V BS is forward bias: this can be intentional for dynamic threshold, or by unintentional voltage drop through R sub (with significant I sub ). The neutral base region is in punchthrough (or breakdown): the depletion region from source and drain merged. Less serious if S/ junction depth is small. The silver lining: the IV snapback during parasitic BJT punchthrough can be used as bistable circuit elements and ES protection devices. R sub I snapback (current not in scale) V S Chapter 5 10
CMOS Latchup Circuit Configuration excerpt from Jan Rabaey Latchup in CMOS (parasitic BJT and resistances between one nmosfet and one pmosfet) Latchup is caused particularly by the special circuit configuration with the positive feedback. The loop gain is larger than one when either npn or pnp V BE is turned on. Notice that any stray current (from radiation, substrate current, stray charge, etc.) can trigger the latchup and cause an effective short between V and GN. Chapter 5 11
ealing with Latchup To prevent parasitic BJT from turning on: lower substrate current (hot-carrier effects) lower parasitic resistance by higher substrate doping and abundance of well/substrate contacts. guard ring to collect carriers, stablize potential and reduce parasitic resistance. This is especially necessary for devices carrying lots of currents or on mixed-signal applications. To prevent latchup by technology twin-well or twin island on SOI substrate to cut the coupling resistance between base and emitter. Many SOI technologies are latchup free. Cut the loop gain by better isolation structures between well and substrates or between wells. Chapter 5 12