FCH9N65F-F85 N-Channel SuperFET II FRFET MOSFET 65 V, 2.6 A, 9 mω Features Typical R DS(on) = 48 mω at = V, I D = A Typical Q g(tot) = 63 nc at = V, I D = A UIS Capability Qualified to AEC Q RoHS Compliant Description SuperFET II MOSFET is ON Semiconductor s brand-new high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. This technology is tailored to minimize conduction loss, provide superior switching performance, dv/dt rate and higher avalanche energy. Consequently SuperFETII is very well suited for the Soft switching and Hard Switching topologies like High Voltage Full Bridge and Half Bridge DC-DC, Interleaved Boost PFC, Boost PFC for HEV-EV automotive. SuperFET II FRFET MOSFET s optimized body diode reverse recovery performance can remove additional component and improve system reliability. G D S Application TO-247 Automotive On Board Charger Automotive DC/DC converter for HEV G D S Maximum Ratings T C = 25 C unless otherwise noted Symbol Parameter Ratings Units V DSS Drain to Source Voltage 65 V Gate to Source Voltage ±2 V I D Drain Current - Continuous ( =) (Note ) 2.6 A Pulsed Drain Current See Fig 4 A E AS Single Pulse Avalanche Rating (Note 2) 4 mj dv/dt MOSFET dv/dt Peak Diode Recovery dv/dt (Note 3) 5 P D Power Dissipation 28 W Derate Above 25 o C.67 W/ o C T J, T STG Operating and Storage Temperature -55 to + 5 o C R θjc Maximum Thermal Resistance Junction to Case.6 o C/W R θja Maximum Thermal Resistance Junction to Ambient (Note 4) 4 o C/W Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FCH9N65F FCH9N65F-F85 TO-247 - - 3 Notes: : Current is limited by bondwire configuration. 2: Starting T J = 25 C, L = 5mH, I AS = 4A, V DD = V during inductor charging and V DD = V during time in avalanche. 3: I SD A, di/dt 2 A/us, V DD 38V, starting T J = 25 C. 4: R θja is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design, while R θja is determined by the board design. The maximum rating presented here is based on mounting on a in 2 pad of 2oz copper. V/ns 24 Semiconductor Components Industries, LLC. September-27, Rev. 2 Publication Order Number: FCH9N65F-F85/D
Electrical Characteristics T J = 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics B VDSS Drain to Source Breakdown Voltage I D = 25μA, = V 65 - - V I DSS Drain to Source Leakage Current On Characteristics Dynamic Characteristics V DS = 65V, T J = 25 o C - - μa = V T J = 5 o C(Note 5) - - ma I GSS Gate to Source Leakage Current = ±2V - - ± na (th) Gate to Source Threshold Voltage = V DS, I D = 25μA 3. - 5. V r DS(on) Drain to Source On Resistance I D = 27A, = V T J = 25 o C - 48 9 mω T J = 5 o C(Note 5) - 346 4 mω C iss Input Capacitance - 2447 38 pf V DS = 25V, = V, C oss Output Capacitance - 2345 348 pf f = MHz C rss Reverse Transfer Capacitance - 3 - pf R g Gate Resistance f = MHz -.5 - Ω Q g(tot) Total Gate Charge - 63 82 nc V DD = 38V Q g(th) Threshold Gate Charge - 4.3 5.6 nc I D = A Q gs Gate to Source Gate Charge - 2.6 - nc = V Q gd Gate to Drain Miller Charge - 28 - nc Switching Characteristics t on Turn-On Time - 4 ns t d(on) Turn-On Delay Time - 25 - ns t r Rise Time V DD = 38V, I D = A, - 4.5 - ns t d(off) Turn-Off Delay Time = V, R G = 4.7Ω - 64 - ns t f Fall Time - 5 - ns t off Turn-Off Time - 69 58 ns Drain-Source Diode Characteristics V SD Source to Drain Diode Voltage I SD = A, = V - -.2 V T rr Reverse Recovery Time I F = A, di SD /dt = A/μs - 4 - ns Q rr Reverse Recovery Charge V DD = 52V - 889 - nc Notes: 5: The maximum value is specified by design at T J = 5 C. Product is not tested to this condition in production. 2
Typical Characteristics POWER DISSIPATION MULTIPLIER.2..8.6.4.2. 25 5 75 25 5 T C, CASE TEMPERATURE( o C) Figure. Normalized Power Dissipation vs. Case Temperature NORMALIZED THERMAL IMPEDANCE, ZθJC 2. DUTY CYCLE - DESCENDING ORDER D =.5.2..5.2. SINGLE PULSE 25 2 5 5 = V 25 5 75 25 5 T C, CASE TEMPERATURE( o C) Figure 2. Maximum Continuous Drain Current vs. Case Temperature P DM t t 2 NOTES: DUTY FACTOR: D = t /t 2 PEAK T J = P DM x Z θjc x R θjc + T C. -5-4 -3-2 - t, RECTANGULAR PULSE DURATION(s) Figure 3. Normalized Maximum Transient Thermal Impedance IDM, PEAK CURRENT (A) 5 = V T C = 25 o C FOR TEMPERATURES ABOVE 25 o C DERATE PEAK CURRENT AS FOLLOWS: I = I 5 - T C 2 25 SINGLE PULSE -5-4 -3-2 - t, RECTANGULAR PULSE DURATION(s) Figure 4. Peak Current Capability 3
Typical Characteristics IS, REVERSE DRAIN CURRENT (A).. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. 2 OPERATION IN THIS AREA MAY BE LIMITED BY RDS(on) = V SINGLE PULSE T J = MAX RATED T C = 25 o C us us ms ms ms Forward Bias Safe Operating Area Figure 6. T J = 25 o C T J = 5 o C T J = -55 o C 6 5 4 3 2 PULSE DURATION = 8μs DUTY CYCLE =.5% MAX V DS = 2V T J = 25 o C T J = 5 o C T J = -55 o C 3 4 5 6 7 8, GATE TO SOURCE VOLTAGE (V) 7 6 5 4 3 2 8μs PULSE WIDTH TJ = 25 o C 5V Top V 8V 7V 6V 5.5V 5V Bottom Transfer Characteristics...3.6.9.2.5 V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 7. Forward Diode Characteristics Figure 8. 3 6 9 2 5 V DS, DRAIN TO SOURCE VOLTAGE (V) 5V Saturation Characteristics 4 35 3 25 2 5 5 8μs PULSE WIDTH TJ = 5 o C 5V Top V 8V 7V 6V 5.5V 5V Bottom 4 8 2 6 2 V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 9. 5V rds(on), DRAIN TO SOURCE ON-RESISTANCE (mω) 8 6 4 2 Saturation Characteristics Figure. ID = A PULSE DURATION = 8μs DUTY CYCLE =.5% MAX T J = 5 o C T J = 25 o C 4 5 6 7 8 9, GATE TO SOURCE VOLTAGE (V) R DSON vs. Gate Voltage 4
Typical Characteristics NORMALIZED DRAIN TO SOURCE ON-RESISTANCE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 3. 2.5 2..5..5. -8-4 4 8 2 6 2 T J, JUNCTION TEMPERATURE( o C) Figure..5..5..95 PULSE DURATION = 8μs DUTY CYCLE =.5% MAX I D = ma I D = A = V Normalized R DSON vs. Junction Temperature.9-75 -5-25 25 5 75 25 5 75 T J, JUNCTION TEMPERATURE ( o C) NORMALIZED GATE THRESHOLD VOLTAGE.2...9.8.7.6 = V DS I D = 25μA.5-8 -4 4 8 2 6 2 T J, JUNCTION TEMPERATURE( o C) Figure 2. Normalized Gate Threshold Voltage vs. Temperature CAPACITANCE (pf) f = MHz = V C iss C oss C rss. V DS, DRAIN TO SOURCE VOLTAGE (V) Figure 3. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature Figure 4. 2. Capacitance vs. Drain to Source Voltage Figure 6. VGS, GATE TO SOURCE VOLTAGE(V) 8 6 4 2 ID = A V DS = 325V V DS = 26V V DS = 39V 2 3 4 5 6 7 Q g, GATE CHARGE(nC) E OSS, [μj] 9.6 7.2 4.8 2.4 4 28 42 56 7 V DS, Drain to Source Voltage [V] Figure 5. Gate Charge vs. Gate to Source Voltage Figure 6. Eoss vs. Drain to Source Voltage 5
I G = const. R G Figure 7. Gate Charge Test Circuit & Waveform R L V V DS DS 9% V DD V DUT % t d(on) t r t d(off) tf t on t off Figure 8. Resistive Switching Test Circuit & Waveforms Figure 9. Unclamped Inductive Switching Test Circuit & Waveforms 6
( Driver ) R G DUT + I SD V DS _ L Driver Same Type as DUT dv/dt controlled by RG I SD controlled by pulse period Gate Pulse Width D = -------------------------- Gate Pulse Period V DD V I FM, Body Diode Forward Current I SD ( DUT ) di/dt I RM Body Diode Reverse Current V DS ( DUT ) Body Diode Recovery dv/dt V SD V DD Body Diode Forward Voltage Drop Figure 2. Peak Diode Recovery dv/dt Test Circuit & Waveforms 7
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