Digital Integrated Circuits A Design Perspective Prentice Hall Electronics and VLSI Series ISBN 0-3-20764-4 [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Copyright 2003 J. Rabaey et al. Why is designing digital ICs different today than it was before? Will it change in future? 2 The First Computer The Babbage Difference Engine (832) 25,000 parts cost: 7,470 3
ENIAC - The First Electronic Computer (946) 4 La Révolution du Transistor Premier transistor Bell Labs, 948 5 The First Integrated Circuits Logique Bipolaire des Années 60 ECL Porte 3-entrées Motorola 966 6
Intel 4004 Micro-processor 97 2300 transistors MHz operation 7 Intel Pentium (IV) Microprocessor 8 Transistor Revolution Transistor Bardeen (Bell labs) in 947 Bipolar transistor Schockley in 949 First bipolar digital logic gate Harris in 956 First monolithic IC Jack Kilby in 959 First commercial IC logic gates Fairchild 960 TTL 962 into the 990 s ECL 974 into the 980 s 9
MOSFET Technology MOSFET transistor - Lilienfeld (Canada) in 925 and Heil (England) in 935 CMOS 960 s, but plagued with manufacturing problems PMOS in 960 s (calculators) NMOS in 970 s (4004, 8080) for speed CMOS in 980 s preferred MOSFET technology because of power benefits BiCMOS, Gallium-Arsenide, Silicon-Germanium SOI, Copper-Low K, 0 Moore s Law In 965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 8 to 4 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 980 s. 2300 transistors, MHz clock (Intel 4004) - 97 6 Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) - 200 40 Million transistor (HP PA-8500) Moore s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 6 5 4 3 2 0 9 8 7 6 5 4 3 2 0 959 960 96 962 963 964 965 966 967 968 969 970 97 972 973 974 975 Electronics, April 9, 965. 2
Transistor Counts K,000,000 00,000 0,000,000 00 Billion Transistors Pentium III Pentium II Pentium Pro i486 Pentium i386 80286 0 8086 Source: Intel 975 980 985 990 995 2000 2005 200 Courtesy, Intel Projected 3 Moore s Law in Microprocessors Transistors (MT) 000 00 0 0. 0.0 0.00 2X growth in.96 years! P6 Pentium proc 486 286 386 8085 8086 4004 80088080 970 980 990 2000 200 Year Transistors on Lead Microprocessors double every 2 years 4 Courtesy, Intel Evolution in DRAM Chip Capacity Kbit capacity/chip 00000000 human memory human DNA 4X growth every 3 years! 64 000 000 0000000 6 000 000 0.07 µm 4 000 000 0. µm 000000 000 000 0.3 µm book 256 000 0.8-0.25 µm 00000 64 000 0.35-0.4 µm 6 000 0000 0.5-0.6 µm 4 000 encyclopedia 0.7-0.8 µm 000 000 2 hrs CD audio.0-.2 µm 256 30 sec HDTV 00.6-2.4 µm 64 page 0 980 983 986 989 992 995 998 200 2004 2007 200 Year 5
Die Size Growth 00 Die size (mm) 0 386 286 8080 8086 8085 8008 4004 P6 486 Pentium proc ~7% growth per year ~2X growth in 0 years 970 980 990 2000 200 Year Die size grows by 4% to satisfy Moore s Law Courtesy, Intel 6 Frequency Frequency (Mhz) 0000 000 00 0 0. Doubles every 2 years P6 Pentium proc 486 8085 386 8086 286 8080 8008 4004 970 980 990 2000 200 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel 7 Power Dissipation Power (Watts) 00 0 8085 8080 8008 4004 8086 286 486 386 P6 Pentium proc 0. 97 974 978 985 992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel 8
Power Will Be a Major Problem Power (Watts) 00000 0000 000 00 0 0. 80858086286 386 486 4004 80088080 Pentium proc 8KW 5KW.5KW 500W 97 974 978 985 992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel 9 Power Density Power Density (W/cm2) 0000 000 00 0 4004 8008 8080 Rocket Nozzle Nuclear Reactor 8086 Hot Plate 8085 286 386 486 P6 Pentium proc 970 980 990 2000 200 Year Power density too high to keep junctions at low temp Courtesy, Intel 20 Not Only Microprocessors Cell Phone Small Signal RF Power RF Units Digital Cellular Market (Phones Shipped) 996 997 998 999 2000 48M 86M 62M 260M 435M Power Management Analog Baseband (data from Texas Instruments) Digital Baseband (DSP + MCU) 2
Major Design Challenges Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions design for test reuse and IP, portability systems on a chip (SoC) tool interoperability Year Tech. Complexity Frequency 3 Yr. Design Staff Size Staff Costs 997 0.35 3 M Tr. 400 MHz 20 $90 M 998 0.25 20 M Tr. 500 MHz 270 $20 M 999 0.8 32 M Tr. 600 MHz 360 $60 M 2002 0.3 30 M Tr. 800 MHz 800 $360 M 22 Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; Chip cost does not increase significantly Cost of a function decreases by 2x But How to design chips with more and more functions? Design engineering population does not double every two years Hence, a need for more efficient design methods Exploit different levels of abstraction 23 Fundamental Design Metrics Functionality Cost NRE (fixed) costs - design effort RE (variable) costs - cost of parts, assembly, test Reliability, robustness Noise margins Noise immunity Performance Speed (delay) Power consumption; energy Time-to-market 24
Cost of Integrated Circuits NRE (non-recurring engineering) costs Fixed cost to produce the design design effort design verification effort mask generation Influenced by the design complexity and designer productivity More pronounced for small volume products Recurring costs proportional to product volume silicon processing also proportional to chip area assembly (packaging) test fixed cost cost per IC = variable cost per IC + ----------------- volume 25 NRE Cost Is Increasing 26 Die Cost Single die Wafer Going up to 2 (30cm) From http://www.amd.com 27
Cost Per Transistor cost: -per-transistor 0. 0.0 0.00 0.000 0.0000 0.00000 Fabrication capital cost per transistor (Moore s law) 0.000000 982 985 988 99 994 997 2000 2003 2006 2009 202 28 Recurring Costs cost of die + cost of die test + cost of packaging variable cost = ---------------------------------------------------------------- final test yield cost of wafer cost of die = ----------------------------------- dies per wafer die yield π (wafer diameter/2) 2 π wafer diameter dies per wafer = ---------------------------------- --------------------------- die area 2 die area die yield = ( + (defects per unit area die area)/α) -α 29 Defects α defects per unit area die area die yield = + α α is approximately 3 4 die cost = f (die area) 30
Yield Example Example wafer size of 2 inches, die size of 2.5 cm 2, defects/cm 2, α = 3 (measure of manufacturing process complexity) 252 dies/wafer (remember, wafers round & dies square) die yield of 6% 252 x 6% = only 40 dies/wafer die yield! Die cost is strong function of die area proportional to the third or fourth power of the die area 3 Some Examples (994) Chip 386DX Metal layers 2 Line width 0.90 Wafer cost $900 Def./ cm 2.0 Area mm 2 43 Dies/ wafer 360 Yield 7% Die cost $4 486 DX2 3 0.80 $200.0 8 8 54% $2 Power PC 60 4 0.80 $700.3 2 5 28% $53 HP PA 700 3 0.80 $300.0 96 66 27% $73 DEC Alpha 3 0.70 $500.2 234 53 9% $49 Super Sparc 3 0.70 $700.6 256 48 3% $272 Pentium 3 0.80 $500.5 296 40 9% $47 32 Reliability Noise in Digital Integrated Circuits Noise unwanted variations of voltages and currents at the logic nodes from two wires placed side by side v(t) capacitive coupling voltage change on one wire can influence signal on the neighboring wire cross talk i(t) inductive coupling current change on one wire can influence signal on the neighboring wire from noise on the power and ground supply rails can influence signal levels in the gate V DD 33
Example of Capacitive Coupling Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology Pulsed Signal 0.2m CMOS 0.6m CMOS Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS From Dunlop, Lucent, 2000 34 Static Gate Behavior Steady-state parameters of a gate static behavior tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances. Digital circuits perform operations on Boolean variables x {0,} A logical variable is associated with a nominal voltage level for each logic state V OH and 0 V OL V(x) V(y) V OH =! (V OL ) V OL =! (V OH ) Difference between V OH and V OL is the logic or signal swing V sw 35 DC Operation Voltage Transfer Characteristics (VTC) Plot of output voltage as a function of the input voltage V(y) V(x) V(y) V OH = f (V IL ) f V(y)=V(x) V M Switching Threshold V OL = f (V IH ) V IL V IH V(x) 36
Mapping Between Analog and Digital Signals V OH V out V OH Slope = - V IH Undefined Region V IL Slope = - 0 V OL V OL V IL V IH V in 37 Noise Margins For robust circuits, want the 0 and intervals to be a s large as possible V DD V DD V OH Noise Margin High Noise Margin Low V OL Gnd Gate Output NM H = V OH -V IH NM L = V IL -V OL "" V IH Undefined Region V IL "0" Gnd Gate Input Large noise margins are desirable, but not sufficient 38 The Regenerative Property A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level v 0 v v 2 v 3 v 4 v 5 v 6 5 v 2 V (volts) 3 v 0 v - 0 2 4 6 8 0 t (nsec) 39
Conditions for Regeneration v 0 v v 2 v 3 v 4 v 5 v 6 v = f(v 0 ) v = finv(v 2 ) v 3 f(v) finv(v) v v finv(v) v 3 f(v) v 2 v 0 v 0 v 2 Regenerative Gate Nonregenerative Gate To be regenerative, the VTC must have a transient region with a gain greater than (in absolute value) bordered by two valid zones where the gain is smaller than. Such a gate has two stable operating points. 40 Noise Immunity Noise margin expresses the ability of a circuit to overpower a noise source noise sources: supply noise, cross talk, interference, offset Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise For good noise immunity, the signal swing (i.e., the difference between V OH and V OL ) and the noise margin have to be large enough to overpower the impact of fixed sources of noise 4 Directivity A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs) Key metrics: output impedance of the driver and input impedance of the receiver ideally, the output impedance of the driver should be zero input impedance of the receiver should be infinity 42
( V ) V o u t Fan-In and Fan-Out Fan-out number of load gates connected to the output of the driving gate gates with large fan-out are slower N Fan-in the number of inputs to the gate gates with large fan-in are bigger and slower M 43 The Ideal Inverter The ideal gate should have infinite gain in the transition region a gate threshold located in the middle of the logic swing high and low noise margins equal to half the swing input and output impedances of infinity and zero, resp. V out R i = R o = 0 g = - Fanout = NM H = NM L = VDD/2 V in 44 An Old-time Inverter V OL =0.45V V OH =3.5V V IL =0.66V V IH =2.35V V M =.64V N MH = N ML = 5.0 4.0 3.0 2.0.0 NM L V M NM H 0.0.0 2.0 3.0 4.0 5.0 V in (V) 45
Delay Definitions V in V out V in input waveform 50% Propagation delay t p = (t phl + t plh )/2 t phl t plh t V out output waveform 50% 90% signal slopes t f 0% t r t 46 Modeling Propagation Delay Model circuit as first-order RC network v out (t) = ( e t/τ )V R v out where τ = RC v in C Time to reach 50% point is t = ln(2) τ = 0.69 τ Time to reach 90% point is t = ln(9) τ = 2.2 τ Matches the delay of an inverter gate 47 Ring Oscillator : Delay Measurement v 0 v v 2 v 3 v 4 v 5 v 0 v v 5 T = 2 t p N 48
A First-order RC Network R v out vin C L E E in = iin ( t) vin( t) dt = V 0 0 dvout CL dt = CLV dv dt V dvout C = i ( t) v ( t) dt C voutdt CL voutdv L C out = L L = out = dt 0 0 0 V 0 out = C V L 2 CLV 2 2 49 Power and Energy Dissipation Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates supply line sizing (determined by peak power) P peak = V dd i peak battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = V dd i(t) P avg = /T p(t) dt = V dd /T i dd (t) dt packaging and cooling requirements Two important components: static and dynamic E (joules) = C L V dd 2 P 0 + t sc V dd I peak P 0 + V dd I leakage f 0 = P 0 * f clock P (watts) = C L V dd2 f 0 + t sc V dd I peak f 0 + V dd I leakage 50 Power and Energy Dissipation Propagation delay and the power consumption of a gate are related Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors the faster the energy transfer (higher power dissipation) the faster the gate For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant Power-delay product (PDP) energy consumed by the gate per switching event An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is Energy-delay product (EDP) = power-delay 2 5
Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 52