International Journal of Electronic Engineering Research ISSN 0975-6450 Volume 2 Number 2 (2010) pp. 159 166 Research India Publications http://www.ripublication.com/ijeer.htm Gain Boosted Telescopic OTA with 110db Gain and 1.8GHz. UGF D. Nageshwarrao 1, S. Venkata Chalam 2 and V. Malleswara Rao 3 1 Nizam Institute of Engg & Tech,Nalgonda(Dt). E-MAIL: deshmukhnag@gmail.com 2 ACE College of Engineering, Hyderabad. 3 Gitam Institute of Technology, Vishakapatnam. Abstract Designing high performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. At large supply voltages, there is a tradeoff among speed, power and gain, amongst other performance parameters. Often these parameters present contradictory choices for the opamp architectures. In this paper we presented the gain boosted telescopic OTA. This architecture achieves a open loop dc gain of 110db and Unity-Gain frequency of 1.8GHz.Apart from we observed phase margin of 62 degree and output voltage swing 1.576V peak-to-peak. Keywords: Telescopic OTA, Two stage amplifier, Cascode amplifier, auxiliary amplifier, gain boostedota. Introduction The evaluation of the microelectronics industry is distinguished by the raising level of integration and complexity. It aims to decrease exponentially the minimum feature sizes used to design integrated circuits. The cost of design is a great problem to the continuation of this evaluation. Owing to the trends towards lower supply voltages with high speed and more accuracy in modern VLSI systems, many well known conventional circuit techniques are no longer applicable. Speed and accuracy are two of the most important properties of analog circuits, however, optimizing circuits for both aspects leads to contradictory demands. In a wide variety of CMOS analog circuits such as switched capacitor filters and pipe line analog to digital converters. Speed and accuracy are determines by the settling behavior of opamp. Fast settling requires a high unity-gain frequency and a single pole settling behavior of the opamp, where as accurate settling requires a high dc gain.
160 D. Nageshwarrao et al The realization of a CMOS opamp that combines high dc gain with high unity-gain frequency has been a difficult problem. The high gain requirements leads to multistage designs with long channel devices biased at low current levels, where as the high unity-gain frequency requirements calls for a single stage design with short channel devices biased at high bias current levels. There have been several circuit approaches to circumvent this problem. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture alternatives, Fig.1 shows some of the most popular topologies. Fig.1 (a) shows the design of a simple two stage amplifier. With all the transistors in the output stage of this amplifier placed in the saturation regime, it has a differential output swing of 2Vsup-4Vds,sat, where Vsup is the supply voltage and Vds,sat is the minimum Vds required to saturate a transistor. For a typical Vds,sat of 200mV, the differential swing is about 2Vsup-0.8V, which is superior to that of most of technologies. Its nondominant pole, arising from its output node, is located at gm6/cl, where gm6 is the transconductance of transistor M5 or M6 and Cl is the load capacitance. Since this pole is determined by an explicit load capacitance, it typically occurs at a relatively low frequency. As a result, this amplifier has a compromised frequency response. Other drawbacks of this simple two stage amplifier are high power consumption because of two stages in its design and poor negative power supply rejection (from Vss) at high frequencies. The folded cascode topology is shown in fig.1(b). The swing of this design is constrained by its cascoded output stage. Although only Vds,sat is needed to saturate the bottom most load transistors and the top most current source transistors, in order to allow for process variations, a small safety margin Vmargin is often added to Vds to ensure saturation. Accounting for these, and the Vds,sat required across the cascode devices, the differential output swing is 2Vsup-8Vds,sat-4Vmargin. With a voltage margin of 100mV, this is estimated to be 2Vsup-2V. The second pole of this opamp is located at gm8/ Cp, where gm8 is the transconductance of transistor M7 or M8 and Cp is the sum of the parasitic capacitance contributed from transistors M2,M8 and M10 at the source of transistor M8. Since its second pole frequency is higher than the nondominant pole of a typical two stage topology, this design has correspondingly superior frequency response. Also because the compensation for this amplifier terminates to ground in contrast to the two stage compensation style, it has better high frequency power supply rejection ratio(psrr). The power consumption of this design is approximately the same as that of the two stage design.
Gain Boosted Telescopic OTA 161 (c) (d) Figure 1: Conventional Operational Amplifier Topologies. (a) Two-stage amplifier. (b) Folded-cascode amplifier., (c)telescopic amplifier (d) No-tail telescopic amplifier A telescopic cascode op-amp, as shown in fig.1(c), typically has higher frequency capability and consumes less power than other topologies. Its high-frequency response stems from the fact that its second pole corresponding to the source nodes of the n-channel cascode devices is determined by the transconductance of n-channel devices as opposed to p-channel devices, as in the case of a folded cascode. Also,the parasitic capacitance at this node arises from only two transistors instead of three, as in the latter. The single stage architecture naturally suggests low power consumption. The disadvantage of a telescopic op-amp is severely limited output swing. It is smaller than that of the folded cascode because the tail transistor directly cuts into the output swing from both sides of the output. In the telescopic op-amp shown in fig.1(c), all transistors are biased in the saturation region. Transistors M1-M2,M7-M8, and the tail current source M9 must have at least Vds,sat to offer good common mode rejection, frequency response, and gain. The maximum differential output swing of a telescopic op-amp is shown to be 2Vsup-10Vds,sat-6Vmargin. Under identical conditions as
162 D. Nageshwarrao et al before, the output swing of this design can be shown to be limited to 2Vsup-2.6V. In a 3-V supply system, this represents a 45% reduction of the available output swing. A large supply voltage, the telescopic architecture becomes the natural choice for systems requiring moderate gain from the op-amp. Reducing supply voltages, on the other hand, forces reconsideration in favor of the folded cascode, or, in the extreme case, the two stage design. Athough a telescopic op-amp without the tail current source[1] fig.1(d) improves the differential swing by 2Vds,sat+ 2Vmargin(600mV), the common mode rejection and power supply rejection of such a circuit is greatly compromised. Moreover, the performance parameters (such as unity-gain frequency and settling time) of an op-amp with no tail or with a tail transistor in the linear region is sensitive to input common mode and supply voltage variation, which is undesirable in most analog systems. Other op-amps that have traditionally been employed in high performance applications include the class AB op-amp[2]. This amplifier, however, requires a minimum supply voltage of 2Vt+4Vds,sat+2Vmargin, where Vt is the threshold. For Vt of 0.8V, Vsup must be greater than 2.6V. This requirement renders these architecture unsuitable in future low voltage applications. Other drawbacks include degraded frequency response because of the presence of current mirrors and large opamp noise. Other rail-to-rail amplifiers with class AB type output stage[3] deliver very high swing. These too, however, typically require current mirrors in the differential path with a high minimum supply-voltage requirement. Why Gain boosted Telescopic OTA? One stage opamps such as telescopic and folded cascode topologies[4] the objective is to maximize the output impendence so as to attain a high voltage gain. The idea behind gain boosting is to further increase the output impedance without adding more cascode devices. Gain boosted OTA [5] has its simplicity over other designs and higher-speed operation because of single-pole roll-off frequency and it has higher power efficiency and lower noise factor compared to folded cascade OTA. NMOS input transistors were chosen as flicker noise will not limit the performance because of its upper cut-off frequency of ~100 KHz. Gain booster enhances the gain without affecting the frequency response of telescopic amplifier. Design of Telescopic OTA with gain boosting The three blocks designed so far, the two folded cascode auxiliary amplifiers(fig2-3) and the main telescopic amplifier(fig1), have been integrated together to form the gain boosted OTA. The schematic is shown in fig.4. The outputs of two folded cascode OTA are connected to the main amplifier as shown to provide the bias and the required gain boosting. As shown in fig.4. during integration of three blocks, at the outputs of the auxiliary amplifiers compensation capacitors have been used in the design to ensure the stability of the system i.e., phase margin greater than 60 o. The values of these
Gain Boosted Telescopic OTA 163 compensation capacitors used in this design are 0.4pF. This value has been decided after a few trails. The W/Ls of the transistors are varied from the theoretically calculated values to ensure the transistors are into saturation. The W/Ls used are shown in the schematics itself beside each transistor. In this design as said, to improve the gain the auxiliary amplifiers are used so that output resistance increases which implies the increase in gain. These auxiliary amplifiers provide the biasing for the main telescopic amplifier (V bn and V bp ). So the common mode voltages for these two auxiliary amplifiers have to maintain at V bn and V bp respectively for bottom and top auxiliary amplifiers. Figure 1: Telescopic OTA. Figure 2: Schematic of Folded Cascode OTA used for nbias (Bottom).
164 D. Nageshwarrao et al Figure 3: Schematic of Folded Cascode OTA used for pbias (Top). Figure 4: Schematic of Gain boosted telescopic OTA. Results The simulated results are generated by 0.18 µm CMOS technology. From the Fig. 5. Open loop DC gain is 110db, unity gain frequency is 1.8GHz and phase margin is 62.4degree. The circuit output voltage swing is 1.576Vp-p. From the results we can say that Gain boosted OTA alone meets all desired specifications. Fig.6. shows the DC response of the Gain boosted Amplifier. As can be seen from Fig.6. the output swing of the amplifier is 1.57V.
Gain Boosted Telescopic OTA 165 Figure 5: AC response of Gain boosted OTA. Figure 6: DC response of gain boosted telescopic OTA. Conclusion With supply voltages becoming more limited, op-amp output swing becomes an extremely critical parameter.while the gain boosted telescopic architecture achieves superior speed and less power consumption. It has a very high output swing. The proposed design combines the high speed, low power advantage of the telescopic architecture with the high swing capability. References [1] G.Nicolini, F.Moretti, and M.Conti, High-frequeny fully differential filter using operational amplifiers without common-mode feedback, IEEE J.Solidstate circuits, Vol.24,pp.803-813, June1989.
166 D. Nageshwarrao et al [2] P.W.Li, M.J.Chin, P.R.Gray, and R.Castello, A ratio independent algorithmic analog-to-digital conversion technique, IEEE J.Solid-state circuits,vol.sc-19,pp.1138-1143, Dec.1984 [3] J.N.Babanezad, A Low-output-impendence fully differential opamp with large output swing and continuous-time common-mode feedback, IEEE J..Solid-state circuits, Vol.26,pp.1825-1833, Dec.1991. [4] R.Jacob Baker, Harry W. Li & David E. Boyce, CMOScircuit design, layout and simulation, IEEE Press Series on Microelectronic Systems, PrenticeHall of India Private Limited, 2004. [5] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill Edition, 2002. D. Nageshwar Rao received the B.E degree in Electronics Engineering from Shyamlal college of Engineering, in 1999 and the M.Tech degree in Electronics and Communication Engineering from J.N.T.U College of Engineering,HYD, in 2004. He currently is pursing the Ph.D degree in Electronics and Communication Engineering at GITAM University, Vishakapatnam. His doctoral research is directed towards the design of a low voltage, low power VLSI analog circuits. S. Venkata Chalam received the B.Tech degree in Electronics and Communication Engineering from J.N.T.U College of Engineering, Ananthapur, and the M.E degree in Electronics and Communication Engineering from faculty of Technology and Engineering, M.S.U,Baroda. He received the Ph.D degree in Electronics and Communication Engineering from J.N.T.U College of Engineering,HYD. His research interests are in the areas of Embeded systems and VLSI. He is now a professor in ACE engineering college.